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The rational finite-register arithmetic code is prefix-free and lossless

Statement

For every configured rational model and fixed frame length in Exact finite-register arithmetic coding for rational block sources, let C(xn) be the codeword assigned to xn by the encoder and put ℓ(xn):=∣C(xn)∣. The codebook on the lexicographically ordered block alphabet [m]n assigns each block a distinct binary word with ℓ(xn)≤B+2 and ℓ(xn)≤−log⁡2pn(xn)+2. The codebook on [m]n is prefix-free, and the decoder returns exactly xn. The configuration-time computation of B terminates. The encoder uses exactly n symbol updates, its bounded integer search terminates, and the decoder reads at most B+2 payload bits per frame without overflow.

Facts & Assumptions

Given: Positive integer frequencies qi, total Q=∑iqi, maximum frame length N, fixed frame length 1≤n≤N, and the encoder/decoder in Exact finite-register arithmetic coding for rational block sources.

[F1]

Finite discrete sources and product blocks: A block probability is pn(xn)=∏t=1npxt.

[F2]

Binary prefix codes and their code trees: A binary code is prefix-free when it is nonsingular and no codeword is a proper prefix of another.

[F3]

Exact finite-register arithmetic coding for rational block sources: The integer endpoint update is L←L+WcxtQn−t and W←Wqxt; the codeword uses u=max⁡{j≤B:2jW≤Qn}, s=u+2, and k=⌊2s(2L+W)/(2Qn)⌋.

[F4]

Information units and logarithm-base convention: log⁡2x=ln⁡x/ln⁡2, with ln⁡2>0.

[F6]

Change of base and inversion of the positive-base real exponential: log⁡2(2v)=v for every real v.

[F7]

Integer part: for every real x there is exactly one integer m with m≤x<m+1: For every real y, ⌊y⌋≤y<⌊y⌋+1.

[F8]

Order, continuity, range, and the product, quotient, and reciprocal laws for the natural logarithm: ln⁡(x/y)=ln⁡x−ln⁡y for positive x,y.

[F9]

Ceilings give the least positive integer meeting a real threshold: For every real x, ⌈x⌉ is an integer with x≤⌈x⌉.

[F10]

Exact finite-register arithmetic coding for rational block sources: The endpoint, width, frequency, and cumulative-frequency registers have B+1 bits; the output index has at most B+2 bits; the temporary register has 2B+4 bits; the counters have the stated ceiling-logarithm widths.

Proof

1.1F1F3giveninduction

After t symbols, the scaled interval for the prefix is [L,L+WQn−t). At t=0 it is [0,Qn), so the claim holds. If it holds at t−1, symbol i occupies the subinterval beginning WciQn−t after the parent lower endpoint and of width WqiQn−t; the widths sum to the parent width because ∑iqi=Q. Thus the update [F3] gives the claimed child interval. At t=n it is [L,L+W) with W=∏t=1nqxt, so after division by D=Qn its width is W/D=pn(xn)>0 by [F1].

2.1F1F3F7step 1.1givenalgebra

The search in [F3] finds u with 2uW≤D<2u+1W: j=0 is admissible since W≤Qn, and D/W≤Qn≤2B, so the largest admissible u is at most B. Hence 2−(u+1)<W/D≤2−u. The selected dyadic cell has width δ=2−(u+2)<W/(2D). Its index k is the floor of 2s times the interval midpoint (2L+W)/(2D); therefore the cell contains that midpoint and extends by at most δ to either side. Since δ is smaller than half the source-interval width, the cell lies inside the source interval. Also the midpoint is in [0,1), so [F7] gives 0≤k<2s and its s-bit representation exists.

3.1F2step 1.1step 2.1given

Length-n source intervals partition [0,1) by step 1.1, and step 2.1 places each nonempty emitted dyadic cell inside its own interval. Thus cells for distinct blocks are disjoint. A proper-prefix relation between emitted words would make one dyadic cell contain the other, which contradicts disjointness. The codewords are distinct and prefix-free by [F2]. A trie leaf therefore identifies one block, so the decoder returns exactly the encoded block.

4.1F3F4F5F6F8F9F10step 1.1step 2.1givenalgebra∎

Since 2u≤D/W, [F4], [F5], and [F6] give u=log⁡2(2u)≤log⁡2(D/W); [F4] and [F8] give log⁡2(D/W)=−log⁡2(W/D)=−log⁡2pn(xn) by step 1.1. Thus the payload length s=u+2 is at most −log⁡2pn(xn)+2. Also W≥1 and D≤QN≤2B, so u≤B and s≤B+2. At configuration, computing P=QN takes N multiplications. The doubling loop for B terminates because 2P≥P for every positive integer P (by induction), and its first B with 2B≥P is least. The encoder performs n updates, tests at most B+1 values of j, and emits at most B+2 bits; the decoder's trie traversal reads at most that many bits and outputs n symbols. Since N≥1, Q≤QN≤2B, so each qi and ci fits its B+1-bit register; also L,W,D≤2B, so their B+1-bit registers suffice. By [F9], if bN=⌈log⁡2(N+1)⌉ and bB=⌈log⁡2(B+3)⌉, then bN≥log⁡2(N+1) and bB≥log⁡2(B+3). Applying the increasing logarithm facts [F4]–[F6] gives 2bN≥N+1 and 2bB≥B+3, so the counters hold counts up to N and output lengths up to B+2. By [F10], the numerator 2s(2L+W) is at most 2B+2⋅3⋅2B<22B+4, so the temporary register suffices; the denominator 2D and scale 2s also fit it. All other products in the interval update are at most D. Hence every loop terminates and no configured per-frame register overflows.

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Cited to discharge well-definedness by Exact finite-register arithmetic coding for rational block sources.

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