A logspace-uniform Boolean circuit family

A Boolean circuit is a finite directed acyclic graph with numbered input nodes, constant nodes, and gates from the fixed basis $\{\mathsf{A}\mathsf{N}\mathsf{D},\mathsf{O}\mathsf{R},\mathsf{N}\mathsf{O}\mathsf{T}\}$; AND and OR gates have two predecessors, NOT gates have one, and constants have values zero or one. Its output is one designated node. A family $(C_n{)}_{n\ge 0}$ has exactly $n$ input nodes labeled $x_1,\dots ,x_n$ in $C_n$ and polynomially many nodes as a function of $n+2$. The family is logspace-uniform when a deterministic read-only-input logspace transducer, on input $1^n$ and a query with binary node indices of length $O(\log (n+2))$, halts and answers the size, gate-type (including input labels and constant values), and predecessor queries for the topologically numbered encoding of $C_n$, and answers which numbered gate is the designated output. In particular, it can stream that polynomial-length encoding without storing it.