Indexed uniform circuits convert to polynomial-time full lists

Fix one valid query to the indexed transducer. Its read-only input and query tapes have polynomially many head positions in $n$, its work tapes use $O(\log (n+2))$ cells over a fixed alphabet, and its finite control has finitely many states. Thus it has at most $(n+2{)}^c$ internal configurations for some fixed $c$. A halting deterministic computation cannot repeat an internal configuration: because the input tapes are read-only and the output tape is write-only, a repetition would repeat the same future transitions forever. Hence each size, type, predecessor, or output query takes polynomial time and writes polynomially many bits.

Query the total node count $N_n\le n+q(n)$ once. For every index $1,\dots ,N_n$, query its type, recording its input label or constant value when applicable, and query every predecessor required by that type; also query the designated output. This includes all $n$ input nodes wherever they occur in the topological order. There are polynomially many queries, each of polynomial time by step 1.1. Every node index is at most $n+q(n)$, so each self-delimiting index has $O(\log (n+q(n)+2))$ bits. Writing the input-count header and all records therefore takes polynomial time and produces a polynomial-length full list.

Each record is the exact gate type, input label or constant value, and predecessor data returned for that same topological node, and the final output field is the exact designated node. The full-list decoder consequently evaluates the same ordered DAG on every input, including the case $n=0$ when the input list is empty.