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LemmaStatement: AI-adaptedProof: AI-generatedPipeline-generated
How statement and proof provenance work

The first chip identifies the source of the statement or construction; the second identifies the source of its local proof or verification.

  • Literature-sourced: the exact statement appears in a cited source; only wording and notation differ.
  • AI-adapted: a semantically identical restatement of literature-sourced material, modulo indexing, notation, and boundary cases adopted by the library.
  • AI-generated: a genuinely novel statement formulated by AI, with no source for the claim itself.

These labels describe origin, not correctness: citations and verification chips remain separate evidence.

A full-list uniform generator bounds circuit size and width

Statement

If the generator in Full-list uniform quantum circuit family halts on input 1n within T(n)≤c(n+1)k transitions, then the generated description has length at most n+T(n)+O(1). Consequently its number of gates and total number of wires are polynomial in n. This is a full-list size bound; it does not establish equivalence with indexed-gate uniformity.

Facts & Assumptions

Given: A full-list family generated by a deterministic one-tape Turing machine G in at most T(n) transitions on input 1n.

[F1]

Full-list uniform quantum circuit family: the output is a complete self-delimiting gate-list description, each gate record has a gate label, and the total wire count is encoded in unary.

[F2]

Deterministic one-tape Turing machines with designated accept and reject states: one transition writes exactly one symbol on the scanned tape cell and moves the head by one cell.

[F3]

Partial functions computed by a machine under fixed encodings: the output is the finite binary word on the final tape, with all later cells blank.

Proof

1.1givenF1F2F3

Initially the input 1n occupies n cells. In T(n) transitions the head visits at most T(n)+1 additional positions, and each transition writes only one symbol by [F2]. At halting, the output convention [F3] therefore gives a binary word of length at most n+T(n)+1. The description is self-delimiting by [F1], so the number of its symbols is bounded by this polynomial quantity.

2.1step 1.1F1algebra∎

Each gate record contains at least one symbol, so its number of gates is no greater than the description length. The total wire count is explicitly unary in the same description, so it too is no greater than the description length. With T(n)≤c(n+1)k, both quantities are O(n+c(n+1)k+1) and hence polynomial in n. The argument makes no claim that an indexed-gate generator can be converted to a full list.

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Sources