How statement and proof provenance work
The first chip identifies the source of the statement or construction; the second identifies the source of its local proof or verification.
- Literature-sourced: the exact statement appears in a cited source; only wording and notation differ.
- AI-adapted: a semantically identical restatement of literature-sourced material, modulo indexing, notation, and boundary cases adopted by the library.
- AI-generated: a genuinely novel statement formulated by AI, with no source for the claim itself.
These labels describe origin, not correctness: citations and verification chips remain separate evidence.
Full-list uniform quantum circuit family
Definition
A full-list uniform quantum circuit family is a sequence together with one fixed deterministic one-tape Turing machine and constants and such that, on input the unary word , halts within transitions and its final tape is a valid self-delimiting binary description of the entire circuit . The machine output convention is that of Deterministic one-tape Turing machines with designated accept and reject states and Partial functions computed by a machine under fixed encodings, and running time is as in Worst-case time and space complexity of a machine.
The following fixed-order code makes the full circuit and its designated input/output wires effective. A unary natural is written , including the one-symbol code for . A self-delimiting binary natural is written , where is its ordinary binary numeral with no leading zeros and . The header gives the input-wire count and total wire count in unary, followed by the gate count as a self-delimiting natural; validity requires .
Each gate record consists of a two-bit label ( for respectively), followed by one self-delimiting wire index for and two ordered self-delimiting indices for CNOT. Every index is less than ; CNOT indices are distinct, with the first the control and the second the target. The list contains exactly records. After the gate list, an output-count self-delimiting natural is followed by that many ordered, pairwise distinct wire indices, each less than . Parsing rejects every other label, malformed or out-of-range index, repeated output index, truncated field, or trailing bit. This defines a total decoder by returning a fixed malformed-code symbol on any invalid word; effective binary encodings and total decoders are as in Effective binary encodings and total decoders.
The gate labels and matrices are the fixed finite library of Clifford+T gate library and exact matrices, with entries in ; CNOT is control-first. The remaining wires are auxiliary wires; their initial states are determined when a family is used in a computation model. This family convention adopts full-list generation. It makes no equivalence claim with indexed-gate uniformity and, in particular, does not assert that an indexed-gate generator can be expanded to the full list in polynomial time.
Remarks
When a family is used in a promise computation, its output predicate is supplied separately by that computation model; the predicate is not an uncharged quantum gate (Finite quantum promise-computation model).
Depends on
- Effective binary encodings and total decoders
- Deterministic one-tape Turing machines with designated accept and reject states
- Partial functions computed by a machine under fixed encodings
- Worst-case time and space complexity of a machine
- Finite circuit syntax and ordered wire labels
- Denotational semantics of a finite layered circuit
- Finite circuit resource accounting
- Clifford+T gate library and exact matrices
Used by
- Bounded-error repetition amplification Algorithm
- Discretized adiabatic path simulation schedule Algorithm
- Five-local history-state adiabatic path Algorithm
- QMA parallel repetition with a midpoint threshold Algorithm
- Adiabatic path access and resource model Definition
- Block-encoding oracle and implementation cost model Definition
- BQP for promise problems in the fixed QC14 model Definition
- Continuous-time Hamiltonian access cost model Definition
- Encoded k-local Hamiltonian promise problem Definition
- EQP on promise problems in the QC14 model Definition
- Finite adiabatic path model Definition
- Finite row-preparation access model for a Szegedy walk Definition
- Hamiltonian simulation error and resources Definition
- Oracle-aware full-list quantum circuit family Definition
- Quantum query algorithm Definition
- Qubitization access model Definition
- Term-list Hamiltonian access Definition
- Uniform verifier interface with a quantum witness Definition
- ZQP on promise problems with bounded failure Definition
- A BQP promise pair with unrestricted off-promise inputs Example
- A full-list uniform generator bounds circuit size and width Lemma
- Boolean circuits compile exactly into the QC14 gate alphabet Lemma
- Uniform interpretation of an input-generated quantum circuit Lemma
- Bounded-error parity query lower bound Theorem
- Circuit-to-adiabatic simulation Theorem
- Finite adiabatic path simulation from term access Theorem
- Sparse Hamiltonian no-fast-forwarding Theorem
Dependency tree · two levels
26 results within two dependency steps of this one, each drawn at its shortest distance from it. An arrow runs from a result to what uses it, so the chart reads left to right and ends at this result, which carries a heavier outline. Every node is a link to that result. Click elsewhere on the chart to enlarge it.
Sources
- John Watrous, Quantum Computational Complexity, Sections III.2 and IV.1 (standard reference, not scraped)
- Ronald de Wolf, Quantum Computing: Lecture Notes, Chapter 13, Section 13.2 (standard reference, not scraped)