Finite circuit syntax and ordered wire labels

Write ${\mathcal{Q}}_n$ for the ordered tensor product of $n$ copies of the two-level register from Finite registers and their ordered computational bases, with ${\mathcal{Q}}_0=\mathbb{C}$. Fix a finite gate alphabet $G$. Each $g\in G$ has an arity $r(g)\ge 1$ and a specified unitary $U_g:{\mathcal{Q}}_{r(g)}\to {\mathcal{Q}}_{r(g)}$. An operation model states which listed gates may be called and what access or cost is assigned to them; the matrix $U_g$ by itself is only the mathematical gate data.

For $n\ge 0$, the circuit wire set is $[n]=\{0,\dots ,n-1\}$ in its displayed order and its state space is ${\mathcal{Q}}_n$. The computational basis word $x=(x_0,\dots ,x_{n-1})$ is assigned slot ${\mathrm{enc}}_n(x)$ from Big-endian encoding of ordered bit strings, so wire $0$ is the most significant bit and the empty register has its single basis vector in slot $0$.

A gate occurrence on the $n$ wires is a pair $(g,(w_0,\dots ,w_{r(g)-1}))$ with distinct wire labels $w_j\in [n]$; the tuple order is the input and output factor order of the local gate. A layer is a finite ordered list of gate occurrences whose wire supports are pairwise disjoint. A unitary circuit is a finite chronological list $L_1,\dots ,L_d$ of such layers, with $L_1$ applied first and $L_d$ last; $d=0$ is the empty circuit. Its input, output, and terminally measured wires are specified as ordered lists without repetitions in $[n]$. This syntax specifies finite data only; the semantic action of gates on the full register is defined separately.