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DefinitionDefinition: Literature-sourcedProof: Not applicablePipeline-generated
How statement and proof provenance work

The first chip identifies the source of the statement or construction; the second identifies the source of its local proof or verification.

  • Literature-sourced: the exact statement appears in a cited source; only wording and notation differ.
  • AI-adapted: a semantically identical restatement of literature-sourced material, modulo indexing, notation, and boundary cases adopted by the library.
  • AI-generated: a genuinely novel statement formulated by AI, with no source for the claim itself.

These labels describe origin, not correctness: citations and verification chips remain separate evidence.

Eigenphase estimation access model

Definition

Let H be a finite-dimensional complex inner-product space, U:H→H a unitary, and ψ∈H a unit vector with a promised phase θ∈[0,1) such that Uψ=exp⁡(2πiθ)ψ. For an integer m≥1, let Q=2m. The phase register is (C2)⊗m with ordered computational basis indexed big-endian by x=∑k=0m−1bk2m−1−k, where bk∈{0,1} (Finite registers and their ordered computational bases, Big-endian encoding of ordered bit strings). Thus the wire of weight 2j is qm−1−j.

There are distinct forward-access options:

  1. Controlled-power access. The model explicitly supplies one controlled U2j operation for each j=0,…,m−1. Each use is counted as one controlled-power query; an implementation's ordinary gate cost is recorded separately.
  2. Single controlled-unitary access. The model supplies calls to C(U)=diag⁡(IH,U) in the control-first order of Controlled Unitary Access. A controlled U2j may be implemented by 2j sequential calls to C(U); those calls are charged individually.

Optional controlled inverse-power access is a separate capability that explicitly supplies C(U−2j) for each required j. It is not implied by either forward option. It is needed only by a consuming procedure that reverses the controlled-power portion of a coherent QPE prefix. Reversing the inverse-QFT gate list does not use U−1.

Finite ordered-register syntax is specified by Finite circuit syntax and ordered wire labels, gate action by Denotational semantics of a finite layered circuit, and projective measurement outcomes by Finite projective measurements. The definition is an access-model promise: it does not assert that the supplied controlled powers have an efficient construction or that θ has an exact m-bit expansion.

Depends on

Used by

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Sources