Circuit Resource Composition

Write $g(A),d(A),w(A)$ for gate count, explicit depth and declared width. Once both blocks are embedded in the declared common physical register, concatenating their schedules uses each gate occurrence and each layer exactly once and in order, so $g(A;B)=g(A)+g(B)$ and $d(A;B)=d(A)+d(B)$. The composite width is the common register's width. It equals $\max (w(A),w(B))$ only when the declared alignment reuses workspace; any wires that must remain allocated are included before taking that maximum.

In the parallel block on disjoint registers, the gate lists and wire sets are disjoint unions, so gate count and width add. Pairing the first layers, then the second layers, and so on, with empty layers on the shorter schedule, gives depth $\max (d(A),d(B))$. On elementary product vectors, the combined circuit acts by the tensor map specified in [A4]; the circuit denotation follows from [A2]. Thus this schedule realizes the stated tensor product without adding operations.

By [F1], a wire is a clean ancilla of the composite block only if the complete composition returns it to zero for every allowed data input. Returning it after $A$ alone does not suffice when $B$ later changes it. Thus an internal wire may be counted clean only after the full block's return condition is checked.