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Five-local history-state adiabatic path

Definition

Input: A full-list uniform circuit on n≥1 qubits with L≥1 listed gates U1,…,UL, each acting on at most two data qubits, and a rational tolerance 0<ε≤1. Circuit products act right to left (Full-list uniform quantum circuit family). The computation is applied to the explicitly supplied all-zero input preparation A0; its wire and preparation cost Cinit is recorded by Circuit-family and computation cost model and Adiabatic path access and resource model. The path-access input also supplies uniform term-time providers for the constructed term list, exact coefficient evaluation, supported time codes and certified call errors required by Discretized adiabatic path simulation schedule.

Output: The explicit finite term list and linearly interpolated Hamiltonian path H(s), together with the supplied initial preparation and resource coordinates, plus the evolution access schedule and data-register output produced by steps 5–7 when the required access providers are available. The schedule uses the declared circuit-family or named-oracle provider for each term call and records its corresponding resource charge.

  1. Set K=⌈2L/ε⌉ and N=L+K. Append K identity gates, writing Uℓ=I for L<ℓ≤N. Use data space (C2)⊗n and an ordered N-qubit clock register (Finite registers and their ordered computational bases, Ordered tensor registers, their inner product, and wire permutations). Its legal unary clock basis is ∣cℓ⟩=∣1ℓ0N−ℓ⟩,0≤ℓ≤N.

  2. Let Hclock=∑j=1N−1∣01⟩⟨01∣clockj,clockj+1 and Hinput=∑i=1n∣1⟩⟨1∣datai⊗∣0⟩⟨0∣clock1,Hclock0=∑j=1N∣1⟩⟨1∣clockj. The first tensor factor is the data register. The zero-summand convention applies when an index range is empty.

  3. For each transition ℓ−1→ℓ, specify two local clock patterns aℓ,bℓ: if 1<ℓ<N, use aℓ=100,bℓ=110 on clock bits (ℓ−1,ℓ,ℓ+1); for ℓ=1, use a1=00,b1=10 on bits (1,2); for ℓ=N, use aN=10,bN=11 on bits (N−1,N). For a clock pattern a, let ∣a⟩⟨a∣ act on those listed clock bits and as identity on all other clock bits. Define the five-local propagation term hℓ=12[Idata⊗(∣aℓ⟩⟨aℓ∣+∣bℓ⟩⟨bℓ∣)−Uℓ⊗∣bℓ⟩⟨aℓ∣−Uℓ∗⊗∣aℓ⟩⟨bℓ∣],Hprop=∑ℓ=1Nhℓ.

  4. Put K0=n+3N and Δ0=1/(216(N+1)3), and choose the positive integer J=2K0+4K02/Δ0+1. Output the linearly interpolated Hamiltonian H(s)=(1−s)Hinit+sHfinal,Hinit=Hinput+Hclock0+JHclock,Hfinal=Hinput+Hprop+JHclock. The term list, integer coefficient J, initial preparation, term-access queries, coefficient bits, gate costs, and generator time are explicit coordinates of the path access model (Adiabatic path access and resource model); no spectral projector supplies A0. With M=n+3N−1 terms, record the rational certificates M1=3N for the derivative and B=M2J2 for every sampled commutator sum; the coefficient functions are the exact constants 1,J and affine functions s,1−s.

  5. Set Δ0=1/[216(N+1)3], γ=3Δ0/4, BT=6N/γ2+63N2/γ3, and T=⌈4BT/ε⌉. Set the finite-precision simulation tolerance to εsim=ε/4. These are finite rational computations.

  6. Invoke Discretized adiabatic path simulation schedule on the constructed path-access instance with evolution time T and tolerance εsim. Its output schedule applies the supplied A0 before the path evolution, using each term's declared circuit-family or named-oracle provider. If any required term provider, coefficient evaluation or supported call is unavailable, return no schedule.

  7. Declare the data register as the output and the clock register as discarded by the output procedure passed to step 6 (the resulting state is the partial trace over the clock, Partial trace over a finite tensor factor). Record T, preparation, simulation calls, coefficient precision, circuit-description and generator costs separately.

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