HHL sparse-query and state-preparation cost

Apply [F1] with $h=1$, valid because $\mathrm{\mid }{H}_{ij}\mathrm{\mid }\le \mathrm{\parallel }H\mathrm{\parallel }\le 1$. The extra padded system labels carry zero eigenvalues; the input remains in the original supported subspace, so its nonzero gap and inverse-state target do not change. The full unitary oracle circuits, controls and reversals act on all physical labels, including invalid labels, as constructed in [F1]; no padded-branch overlap contributes a matrix value.

Put $\eta =ϵ\mathrm{/}(8192\kappa L)$. For each phase time $t_j$, certified arithmetic selects a rational $q_j\in [0,t_j]$ with $t_j-q_j\le \eta \mathrm{/}2$ and a rational simulator tolerance ${\zeta }_j$ with $\eta \mathrm{/}4\le {\zeta }_j\le \eta \mathrm{/}2$; their construction cost remains in the separately charged arithmetic/phase-generation coordinates. Invoke QA25 at rational signed time $-q_j$ and tolerance ${\zeta }_j$. By [F2], its clean-input error from $e^{+iH{q}_j}$ is at most ${\zeta }_j$, and by [F6]–[F7] the time-rounding error from $e^{+iH{t}_j}$ is at most $t_j-q_j$. Thus each effective forward call has clean-input error at most $\eta$. Use its actual adjoint for the reverse call; [F3] gives the same clean-input error without assuming full-space accuracy on dirty inputs. The $2L$ effective errors sum to $ϵ\mathrm{/}(4096\kappa )$ as required in OP5, so [F5] applies with the stated state and failure guarantees.

In one $V$ or $V^{†}$, sum the loose signal-call bound in [F2] over all signed rational times $\pm q_j$. Since $q_j\le t_j$, their absolute values sum to less than $2t_0$ by [F4], so this uses $O(d{t}_0+L\log (32768\kappa L\mathrm{/}ϵ))$ signal calls; also ${\zeta }_j\ge \eta \mathrm{/}4$ makes $\log (1\mathrm{/}{\zeta }_j)=O(\log (1\mathrm{/}\eta ))$. Multiplying by [F1]'s location/value conversion and then by the at most $2RK$ preparation/inverse-preparation calls gives $O\text{\hspace{0.17em}⁣}(R\kappa [d{t}_0+L\log (32768\kappa L\mathrm{/}ϵ)]\log (d+1))$ sparse-oracle calls, with a possibly smaller constant value-query count. Literal reversals and coherent controls change only constants already covered by [F1]–[F3].

Since $T<16(t_0+1)$, $L=O(\log (2+\kappa \mathrm{/}ϵ))$. With $d,\kappa \ge 1$, $0<ϵ\le 1$, and $t_0=2048\kappa \mathrm{/}ϵ$, the expression in step 3.1 is $O(d{\kappa }^2{ϵ}^{-1}(1+\log (1\mathrm{/}\rho ))\mathrm{polylog}(2+d\kappa \mathrm{/}ϵ))$. For fixed constant $\rho$ this gives the displayed order. The separate $B$ and $B^{†}$ counts are at most $RK$ each by [F4]. Padding only appends clean high index bits to their input/output register convention; no extra sparse query is needed for this embedding. Their actual implementation and any controls used remain charged as supplied costs. All other direct-simulation resource coordinates stay in [F4]'s explicit sum, so no table, phase-generation, gate or bit-time claim is inferred from the sparse-query bound.