LemmaStatement: Literature-sourcedProof: AI-adaptedPipeline-generatedjudge pass (gpt-6-luna)

How statement and proof provenance work

The first chip identifies the source of the statement or construction; the second identifies the source of its local proof or verification.

Literature-sourced: the exact statement appears in a cited source; only wording and notation differ.
AI-adapted: a semantically identical restatement of literature-sourced material, modulo indexing, notation, and boundary cases adopted by the library.
AI-generated: a genuinely novel statement formulated by AI, with no source for the claim itself.

These labels describe origin, not correctness: citations and verification chips remain separate evidence.

Clean reversible controlled multiplication by a cyclic constant

Statement

Let $G = ⟨ g ⟩$ have order $q \geq 2$ , let $c \in G$ , and let valid fixed-length codes occupy a subset $V \subseteq {0, 1}^{w}$ . Suppose total Boolean circuits are supplied for functions $h_{c}, h_{c^{- 1}} : {0, 1} \times {0, 1}^{w} \to {0, 1}^{w}$ , where $h_{c} (b, z) = {\begin{cases} z, & b = 0, \\ enc (u c), & b = 1, z = enc (u) \in V, \\ z, & b = 1, z \notin V, \end{cases} .$ For each fixed control $b$ , the maps $z \mapsto h_{c} (b, z)$ and $z \mapsto h_{c^{- 1}} (b, z)$ are inverse permutations; the full controlled permutation preserves $b$ . Then reversible embedding supplies a clean-ancilla circuit that acts on a control bit and accumulator by

∣ b, z, 0_{w o r k} ⟩ ⟼ ∣ b, h_{c} (b, z), 0_{w o r k} ⟩ .

If the two Boolean circuits have at most $S$ non-input nodes and $E$ port uses each, the construction uses at most $12 S + 8 E + 5 w$ elementary gates and at most $2 (S + E) + w$ clean work wires. The gate charge counts each supplied $X$ , CNOT, and Toffoli as one gate; no cost for constructing the Boolean descriptions is inferred.

Facts & Assumptions

Given: A finite cyclic group and fixed element $c$ , valid codes $V$ , total Boolean functions $h_{c}, h_{c^{- 1}}$ whose fixed-control slices are inverse permutations with the displayed action, and their explicit Boolean circuit descriptions.

[F1]

Finite cyclic discrete-logarithm problem and costed encoding: valid element codes are injective fixed-length bit strings, and operation circuits and costs are supplied as input data.

[F2]

Reversible embedding of a Boolean circuit: a finite Boolean DAG can be evaluated into fresh work, its outputs XORed into a target, and its evaluation reversed.

[F3]

Gate, workspace, and serial-depth costs of reversible embedding: the reversible embedding restores all clean work to zero and uses at most $6 S + 4 E + m$ gates and $S + E$ work bits for an $m$ -bit output.

[F4]

CNOT and Control-Target Order: CNOT on an ordered control and target bit maps $(a, b)$ to $(a, b \oplus a)$ .

[F5]

Clean and dirty ancillas: a clean work register must return exactly to its specified zero vector.

[F6]

Denotational semantics of a finite layered circuit: a chronological finite gate list acts by the corresponding composed unitary, with later gates on the left.

[F7]

The computational basis is orthonormal: distinct computational-basis words are orthonormal.

Proof

1.1givenF1algebra

For a valid code $z = enc (u)$ , the inverse property gives $h_{c^{- 1}} (1, h_{c} (1, z)) = z$ and $h_{c} (1, h_{c^{- 1}} (1, z)) = z$ ; for invalid $z$ both maps fix $z$ , and for $b = 0$ both fix $z$ . Thus, for each fixed control $b$ , the two supplied maps on the $w$ -bit data register are inverse permutations on every data word, and the complete controlled map preserves $b$ .

1.2F2F3

Apply [F2] to $h_{c}$ and $h_{c^{- 1}}$ with separate fresh $w$ -bit targets. By [F3], each XOR computation returns its internal work to zero and has at most $6 S + 4 E + w$ gates and $S + E$ work bits.

2.1step 1.2F4F6F7algebra

Starting from control $b$ , data code $z$ , and a fresh target $t = 0^{w}$ , compute $h_{c} (b, z)$ into $t$ . Swap $z$ and $t$ bitwise using three CNOTs per bit; on each pair $(u, v)$ the sequence $(u, v) \mapsto (u, u \oplus v) \mapsto (v, u \oplus v) \mapsto (v, u)$ , so it swaps the registers. The accumulator now contains $h_{c} (b, z)$ and $t$ contains the old $z$ .

2.2step 1.1step 1.2F3F5F6algebra

Compute $h_{c^{- 1}} (b, h_{c} (b, z))$ into the old- $z$ target by XOR. By step 1.1 this XORs $z$ with itself and clears $t$ to $0^{w}$ . The inverse computation also restores its internal work to zero by [F3]. The resulting data is $h_{c} (b, z)$ , with every work and temporary target bit zero, which is the clean-ancilla identity of [F5].

3.1step 1.2step 2.2F3algebra∎

The forward and inverse embeddings use at most $12 S + 8 E + 2 w$ gates in total; the three-CNOT swaps use $3 w$ more. The two Boolean embeddings use at most $2 (S + E)$ clean internal work bits and the swapped $w$ -bit target is also clean on return. Hence the total bounds are $12 S + 8 E + 5 w$ gates and $2 (S + E) + w$ clean work wires.

Depends on

Used by

Costed coherent evaluation of cyclic group powers Algorithm
Correctness and clean-work cost of cyclic power evaluation Theorem

Dependency tree · two levels

31 results within two dependency steps of this one, each drawn at its shortest distance from it. An arrow runs from a result to what uses it, so the chart reads left to right and ends at this result, which carries a heavier outline. Every node is a link to that result. Click elsewhere on the chart to enlarge it.

Sources

John Preskill, Quantum Computation, Chapter 5: Classical and Quantum Circuits (standard reference, not scraped)
Ronald de Wolf, Quantum Computing: Lecture Notes, arXiv:1907.09415v6 (standard reference, not scraped)