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TheoremStatement: Literature-sourcedProof: AI-generatedPipeline-generatedprecheck pass
How statement and proof provenance work

The first chip identifies the source of the statement or construction; the second identifies the source of its local proof or verification.

  • Literature-sourced: the exact statement appears in a cited source; only wording and notation differ.
  • AI-adapted: a semantically identical restatement of literature-sourced material, modulo indexing, notation, and boundary cases adopted by the library.
  • AI-generated: a genuinely novel statement formulated by AI, with no source for the claim itself.

These labels describe origin, not correctness: citations and verification chips remain separate evidence.

Gate, workspace, and serial-depth costs of reversible embedding

Statement

Let n,m≥0, x∈{0,1}n, and y∈{0,1}m. Let a finite topologically ordered Boolean DAG have S non-input nodes, including constants, and E input-port uses counted with multiplicity. Its gates are NOT, AND, OR, and constants, with fan-in at most two, and it has m ordered output ports computing f(x). Under the fixed elementary alphabet in Finite circuit resource accounting, counting each occurrence of X, CNOT, and Toffoli as one gate and one serial layer, Reversible embedding of a Boolean circuit returns a circuit on the ordered input, target, and work registers implementing

∣x,y,0w⟩⟼∣x,y⊕f(x),0w⟩

for every basis input x and every target string y. It uses at most 6S+4E+m elementary gate occurrences, at most S+E clean work bits, and serial depth at most 6S+4E+m. The same operator action holds coherently on arbitrary superpositions and after adjoining any finite reference register.

Facts & Assumptions

Given: The finite Boolean DAG convention, the procedure in Reversible embedding of a Boolean circuit, and the gate actions in the local suppliers. Prove correctness, clean-work restoration, and the stated bounds.

[F1]

Boolean circuits: basis, fan-in, size, and depth: A Boolean circuit has constants 0 and 1, and NOT, AND, and OR gates; AND and OR have fan-in two, while NOT has fan-in one. Its size is its number of non-input gates.

[F2]

Reversible embedding of a Boolean circuit: The procedure computes each gate into fresh zero work, copies the designated outputs into arbitrary targets, and reverses the node-evaluation list.

[F3]

Fresh-target NOT and OR gadgets: The fresh-target sequences write 1⊕a for NOT and a⊕b⊕ab=a∨b for OR without changing sources.

[F4]

Toffoli computes into a clean target and uncomputes it: Toffoli computes ab into a clean target, and copying followed by the inverse Toffoli restores that target to zero.

[F5]

Clean and dirty ancilla identities extend to references and mixed states: Clean workspace identities extend to arbitrary references and matrices.

[F6]

X, CNOT, Toffoli, and Fredkin are involutions: X, CNOT, and Toffoli are each their own inverse.

[F8]

The Pauli matrices: The Pauli matrix X=(0110) sends ∣0⟩ to ∣1⟩ and ∣1⟩ to ∣0⟩.

[F7]

Ordered tensor registers, their inner product, and wire permutations: An ordered tensor register retains the displayed factor order, and its product basis is ordered lexicographically by factor-index tuples.

[F9]

Big-endian encoding of ordered bit strings: The first bit is the most significant position in the computational-basis index.

[F10]

Big-endian bit-string indices are bijective: Each length-n bit string labels exactly one computational-basis vector of the n-qubit register.

[F11]

Denotational semantics of a finite layered circuit: A chronological list of layers L1,…,Ld, with L1 applied first, denotes ULd⋯UL1.

[F12]

The product basis is orthonormal and tensor dimensions multiply: The ordered tensor-product computational basis is orthonormal, including the work-register factors.

[F13]

Finite circuit resource accounting: Circuit size counts gate occurrences, depth counts explicit layers, and width counts all wires including workspace wires.

Proof

1.1givenF1F2F3F4F13algebra

Let q be the number of two-port nodes whose two ports name the same source. Each non-input node uses at most three evaluation gates: at most one for a constant, two for NOT, one for AND, and three for OR. Each repeated-source node adds one CNOT copy and one uncopy, so the forward pass uses at most 3S+2q gates. Since each such node accounts for two of the E port uses, q≤E, and the forward bound is at most 3S+2E. It uses S value bits and q≤E temporary bits.

2.1givenF2F4F6F11F13step 1.1algebra

The m output ports are copied by m CNOTs into distinct target bits. Reversing the complete node-evaluation list uses at most another 3S+2E gates. By [F6], each gate is its own inverse; reversing both order and gate sequence therefore implements the inverse computation and returns every value and temporary bit to zero. The total is at most 2(3S+2E)+m=6S+4E+m gate occurrences. A serial execution assigns each occurrence its own explicit layer, so the depth has the same bound by [F13]; [F11] specifies the chronological operator product.

3.1givenF1F2F3F4F6F7F8F9F10F11F12step 2.1inductionalgebra

Use [F9]–[F10] to identify each ordered bit string with its unique basis vector. Induct along the supplied topological order. A constant-0 node leaves its zero bit unchanged and a constant-1 node uses [F8]; NOT and OR nodes receive the outputs in [F3], and AND nodes receive the output in [F4]. If a two-port node repeats a source value c, its fresh scratch bit is set to c by CNOT; the two distinct physical control wires then both hold c, so AND gives c∧c=c and OR gives c∨c=c. The scratch is immediately uncomputed by the same CNOT. Thus every value bit equals its Boolean node value and all temporary bits are zero before the output copy. The m output CNOTs produce y⊕f(x); reversing the node list then restores every work bit without touching the input or target registers, whose order is fixed by [F7]. Since applying y↦y⊕f(x) twice returns y, the target action is a permutation of the ordered basis and is unitary by [F12]; the compiled gate list is unitary by [F6] and [F11].

4.1step 3.1F5algebra∎

The basis identity in Step 3.1 extends by linearity to every input vector, so it is the clean-ancilla identity required by [F5]. The lemma then extends it to every finite reference register and every matrix, hence to density matrices. The construction uses only the supplied finite list; no choice principle is used.

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Sources