TheoremStatement: Literature-sourcedProof: AI-generatedPipeline-generatedprecheck pass

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Compute-copy-uncompute yields a clean coherent function query

Statement

Let $f : {0, 1}^{a} \to {0, 1}^{b}$ be total. Suppose a finite nonoracle gate circuit $V$ preserves the address and, from zero value and workspace registers, computes

V ∣ x ⟩ ∣ 0^{b} ⟩ ∣ 0^{w} ⟩ = ∣ x ⟩ ∣ f (x) ⟩ ∣ 0^{w} ⟩

for every $x$ , with gate count $G$ . Suppose its exact inverse circuit is available with the same gate count and acts only on the address, value, and workspace registers. Applying $V$ , copying the $b$ output bits to a fresh target by $b$ CNOTs, and applying $V^{- 1}$ implements the standard query, restores the value and workspace registers to zero, and uses exactly $2 G + b$ gate occurrences. Any query calls in a different implementation must be charged separately.

For a finite Boolean DAG with $S$ noninput nodes, $E$ input-port uses counted with multiplicity, and $b$ ordered output ports, the current QC10 reversible-embedding construction itself already implements the clean XOR query. Its local cost theorem gives at most $6 S + 4 E + b$ gates and $S + E$ clean work bits. Thus its size is $O (S + E + b)$ , and is $O (S + b)$ when $E = O (S)$ , as for the stated bounded-fan-in graphs. No depth bound is inferred from the classical Boolean DAG.

Facts & Assumptions

Given: A total function, a clean reversible evaluator with an exact same-count inverse, a fresh target register, and the QC10 Boolean-DAG supplier for the concrete cost statement. The operation model's declared finite nonoracle gate alphabet contains and permits CNOT for the generic copy step; $V$ and its exact inverse are available as circuits over that model. For the concrete QC10 cost claim, it contains and permits $X$ , CNOT and Toffoli, each counted as one nonoracle gate occurrence. Any black-box query calls are charged separately.

[F1]

Clean and dirty ancillas: a clean workspace initialized at zero must return exactly to zero for every allowed data input.

[F2]

Inverse Unitary Access: the inverse circuit applies the gate inverses in reverse chronological order; its availability and charge are explicit.

[F3]

CNOT and Control-Target Order: CNOT from a control bit $r$ to a distinct target bit $y_{j}$ maps $∣ r, y_{j} ⟩$ to $∣ r, y_{j} \oplus r ⟩$ .

[F4]

Standard bit-flip query convention: the desired standard action is $∣ x ⟩ ∣ y ⟩ \mapsto ∣ x ⟩ ∣ y \oplus f (x) ⟩$ .

[F5]

Reversible embedding of a Boolean circuit: the QC10 procedure evaluates each Boolean-DAG node into work bits, copies the ordered output ports into the target, and reverses its evaluation list.

[F6]

Gate, workspace, and serial-depth costs of reversible embedding: for the specified DAG and gate model, that procedure implements the standard XOR action with clean work and at most $6 S + 4 E + b$ gates and $S + E$ work bits.

[F7]

Finite circuit resource accounting: gate size counts each occurrence; oracle calls, depth, width, and other costs are separate coordinates.

[F8]

Finite registers and their ordered computational bases, The computational basis is orthonormal and The product basis is orthonormal and tensor dimensions multiply: the ordered basis vectors of the joint address, value, workspace and target registers form a complete basis.

Proof

1.1givenF1

On basis input $∣ x ⟩ ∣ 0^{b} ⟩ ∣ 0^{w} ⟩ ∣ y ⟩$ , the first circuit $V$ produces $∣ x ⟩ ∣ f (x) ⟩ ∣ 0^{w} ⟩ ∣ y ⟩$ by the assumed evaluator identity. The output register is a separate factor from the fresh target.

2.1step 1.1F3algebra

Applying one CNOT from each output bit to its corresponding target bit leaves $x$ , $f (x)$ , and the zero workspace unchanged, and changes $y$ to $y \oplus f (x)$ by [F3].

3.1givenstep 2.1F1F2F4F7algebra

Apply $V^{- 1}$ to the address, value, and workspace factors. Since $V^{- 1} V = I$ on those factors and does not act on the target, the result is $∣ x ⟩ ∣ 0^{b} ⟩ ∣ 0^{w} ⟩ ∣ y \oplus f (x) ⟩$ . This is the standard query action [F4] with clean work [F1]. The gate count is $G + b + G = 2 G + b$ by [F2] and [F7].

4.1step 3.1F1F4F8algebra

The basis vectors with value and work initially zero span the allowed input subspace by [F8]. The composed circuit is linear, so step 3.1 extends to every superposition in that subspace. Thus the standard query action and clean-work identity hold for all allowed vector inputs.

5.1F5F6algebra∎

The finite Boolean-DAG procedure [F5] already includes its own output copy and reverse pass. Therefore its complete elementary gate-occurrence bound for implementing the XOR action is the supplier bound [F6], not an additional application of the generic $2 G + b$ construction. The stated asymptotic forms follow by dividing the exact bound by the indicated parameter relation $E = O (S)$ when that relation holds.

Depends on

Used by

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Sources

Andrew M. Childs, Lecture Notes on Quantum Algorithms (17 April 2025) (standard reference, not scraped)
Ronald de Wolf, Quantum Computing: Lecture Notes (arXiv:1907.09415v6) (standard reference, not scraped)