How statement and proof provenance work
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These labels describe origin, not correctness: citations and verification chips remain separate evidence.
Reversible Computation, Ancillas, and Coherent Oracles
1 · Prerequisites
- Absolute and Conditional Convergence; Rearrangement; Products
- Binary Operations, Monoids, Groups and Subgroups
- Boolean Circuits and Nonuniform Complexity
- Bounded Linear Operators and Quotient Spaces
- Circuit Syntax, Denotational Semantics, and Measurement
- Compactness in Metric Spaces
- Completeness, Completion, and Uniform Continuity
- Complex Norms and Realification
- Complexification, Realification and Real Structures
- Construction of the Natural Numbers
- Construction of the Real Numbers via Cauchy Sequences
- Construction of the Real Numbers via Dedekind Cuts
- Continuity, IVT, EVT, and Uniform Continuity
- Controlled Gates, Phase, and Entanglement
- Cosets, Index and Lagrange's Theorem
- Countability and Uncountability
- Determinants of Matrices over a Commutative Ring
- Divisibility, Euclidean Domains, Principal Ideal Domains and Unique Factorisation
- Dual Spaces, Bilinear and Quadratic Forms, and Sylvester's Law of Inertia
- Filters and Ultrafilters
- Finite Counting, Factorials and Binomial Coefficients
- Finite Dimensional Normed Spaces and Riesz Lemma
- Finite-Dimensional Complex Inner-Product Spaces and Matrix Interfaces
- Foundations of the Real Numbers for Analysis
- Free Modules, Exact Sequences, Projective and Injective Modules
- Fundamental Trigonometric Identities
- Group Actions, Orbits, Stabilisers and Cayley's Theorem
- Group Homomorphisms and the Isomorphism Theorems
- Hilbert Space Geometry and Riesz Representation
- Ideals, Quotient Rings and the Isomorphism Theorems for Rings
- Inner Product Spaces, Gram-Schmidt, Projections and Adjoints
- Limits of Real Functions
- limsup, liminf, and Subsequential Limits
- Linear Independence, Bases and Dimension
- Linear Transformations, Rank-Nullity and Quotient Spaces
- Matrices, the Matrix of a Linear Map, and Change of Basis
- Metric Spaces
- Modules, Submodules, Quotient Modules and the Isomorphism Theorems
- Monotone Functions, Discontinuities, and Continuity Sets
- Monotone Sequences, Bolzano-Weierstrass, and Cauchy Completeness
- Normal Subgroups and Quotient Groups
- Normed and Banach Spaces
- Order, Zorn's Lemma, and the Axiom of Choice
- Polynomial Rings, the Division Algorithm and Roots
- Power Series and Real-Analytic Functions
- Properties of the Integral and the Working FTC
- Pure and Mixed States, Ensembles, and Schmidt Decomposition
- Qubits, Bloch Sphere, Pauli Algebra, and One-Qubit Gates
- Registers, Tensor Products, and Partial Trace
- Relations, Functions, and Quotients
- Rings, Subrings, Integral Domains and Fields
- Rⁿ as a Normed Space; Vector-Valued Functions
- Roots, Rational Powers, and Classical Inequalities
- Sequences and Limits
- Sequences and Series of Functions; Uniform Convergence
- Series: Convergence and the Nonnegative Tests
- Simple Field Extensions and the Construction of the Complex Numbers
- Sine, Cosine, and the Definition of Pi
- Strongly Continuous Semigroups and Hille Yosida
- Suprema and Infima
- Symmetric Groups, Cycle Decomposition and the Sign Homomorphism
- Tensor Products of Modules
- The Complex Exponential and Euler's Formula
- The Derivative and the Mean Value Theorems
- The Determinant of a Linear Operator, Cofactors and Cramer's Rule
- The Exponential Function
- The Riemann Integral: Definition and Integrability
- The Spectral Theorem, Positive Operators and Singular Value Decomposition
- The ZFC Axioms and the Basic Set Constructions
- Topology of ℝ
- Vector Spaces, Linear Subspaces, Span and Direct Sums
2 · Summary
This page develops reversible Boolean computation with explicit finite circuits and ordered input, work, and target registers. It defines clean and dirty ancilla contracts, Toffoli and Fredkin actions, the compute-copy-uncompute procedure, and a coherent XOR function oracle. The local results prove gate identities, coherent correctness, workspace restoration, and gate/work/depth costs. Oracle invocations, explicit circuit compilation, and controlled access remain distinct resource assumptions.
3 · Logical flowchart
4 · Definitions, theorems and proofs
Clean and dirty ancillas
Definition
Let be a finite ordered quantum register and let be an ordered register of ancilla qubits, with Hilbert spaces and . Write , including when . Let be a unitary on and let be a unitary on .
The register is a clean ancilla register for and when
for every vector . Thus the data operation is independent of the input vector and all clean wires return exactly to zero.
The register is a dirty ancilla register for and when the operator identity holds on . Equivalently, every product input is mapped to , with the same for every data and ancilla vector. This requires exact restoration of an arbitrary, initially unknown ancilla state and forbids residual data–ancilla correlation.
These are exact contracts for the complete subroutine. A temporary intermediate alteration of an ancilla is permitted if the full unitary satisfies the stated identity.
Remarks
The reference-register and arbitrary-matrix consequences are proved in Clean and dirty ancilla identities extend to references and mixed states.
Toffoli and Fredkin gates
Definition
All bits are in , with addition denoted by and multiplication by juxtaposition. On three distinct ordered computational-basis wires, define the Toffoli gate and Fredkin gate by
and
These basis actions extend linearly. Wire order is exactly the order displayed; the first two wires of are controls and the third is its target, while the first wire of is its control and the other two are conditionally swapped. Negative-control variants mean conjugating the chosen positive control by before and after the gate. These are fixed arity-three labels in the declared finite gate alphabet, not implicit access to arbitrary multicontrol gates. Their reversibility is established in X, CNOT, Toffoli, and Fredkin are involutions ↗.
Clean and dirty ancilla identities extend to references and mixed states
Statement
Let and satisfy either the clean or dirty identity in Clean and dirty ancillas, and let be any finite ordered reference register. Put , where the rank-one operator notation used here is defined by . In the clean case, for every matrix on ,
In the dirty case, for every matrix on ,
Thus the stated identities apply in particular to density matrices, meaning positive semidefinite matrices of trace one.
Facts & Assumptions
Given: Finite-dimensional registers , ordered so the operation acts on and as the identity on . Prove the stated extension in the clean and dirty cases.
Clean and dirty ancillas: In the clean case, for every . In the dirty case, .
Tensor products of finitely many linear maps: For a finite ordered family of linear maps, the tensor map is the unique linear map whose action on each elementary tensor is the tensor of the factor-map actions.
Ordered tensor registers, their inner product, and wire permutations: The tensor inner product on elementary tensors is the product of the factor inner products, with the displayed register order retained.
The product basis is orthonormal and tensor dimensions multiply: For finite ordered registers with specified orthonormal factor bases, the lexicographically ordered elementary tensors form an orthonormal basis and therefore span the product register.
Proof
In the clean case, for every , write as a finite sum of elementary tensors. The clean identity in [F1] and the tensor-map rule [F2] give .
For any linear map with adjoint and vectors , conjugate symmetry and the defining adjoint relation give for every . Hence . By [F3], . Apply the rank-one identity with , , and , where range over the product orthonormal basis of . Step 1.1 gives the clean conjugation formula for each . Every matrix on equals , since the right side agrees with on each basis vector; hence these matrix units span and linearity proves the clean identity for every .
In the dirty case, [F1] and [F2] give on every elementary tensor and hence on the whole product space. The product inner product [F3] makes its adjoint : this follows first on elementary tensors from the defining adjoint relation for , then on all vectors because they span by [F4]. Substitution yields the dirty identity for every matrix , including every density matrix; for a product , the output is , so the dirty factor remains unchanged and uncorrelated in this product case.
X, CNOT, Toffoli, and Fredkin are involutions
Statement
On the ordered computational basis, , CNOT, Toffoli , and Fredkin are involutions. Their linear extensions are unitary. With chronological order meaning the gates are applied in the written order, Fredkin is implemented by CNOT, then , then CNOT.
Facts & Assumptions
Given: The displayed gate actions and the ordered tensor-product computational basis. Prove involutivity, unitarity, and the stated Fredkin implementation.
The Pauli matrices: In the ordered computational basis, .
CNOT and Control-Target Order: In the ordered two-qubit basis, .
Toffoli and Fredkin gates: ; and .
The computational basis is orthonormal: For every , the ordered computational basis of is an orthonormal basis for its declared inner product.
The product basis is orthonormal and tensor dimensions multiply: The elementary tensors of specified ordered orthonormal factor bases, in lexicographic order, form an orthonormal basis of the tensor register.
Denotational semantics of a finite layered circuit: A chronological list of layers , with applied first, denotes .
Proof
The matrix in [F5] sends to . Applying it twice sends to , so .
By [F1], applying CNOT twice sends to , so .
Applying twice leaves unchanged and sends to . Thus .
When the Fredkin control is , each application fixes . When it is , each application swaps and leaves the control unchanged. In either case two applications restore all three bits, so .
The four maps permute the ordered orthonormal computational basis by [F1]–[F5]. A permutation of an orthonormal basis preserves inner products, so each linear extension is unitary; by Steps 1.1–1.4 each is its own inverse.
Apply the gates chronologically as prescribed by [F6] to . After CNOT the last two bits are . If , Toffoli does nothing and the last CNOT restores . If , Toffoli changes its target to , and the last CNOT changes the other bit to . Thus the output is for and for , exactly the Fredkin action.
Reversible embedding of a Boolean circuit
Definition
Inputs are integers , distinct ordered Boolean input wires, an -bit target register disjoint from the input wires, and a finite Boolean DAG with an explicit topological order and an ordered list of exactly output ports. Every vertex has a unique identifier; each non-input node is a constant or , a NOT node of fan-in one, or an AND or OR node of fan-in two. Each source reference must name an input vertex or an earlier node in the supplied order. Each output port may name any input or non-input node, and repeated output ports are allowed. The Boolean graph uses the NOT/AND/OR basis with constants from Boolean circuits: basis, fan-in, size, and depth, extended here to multiple ordered output ports sharing one graph.
Return INVALID if the input wires or graph vertices do not have distinct identifiers, a target wire overlaps an input or graph vertex, an unsupported gate or incorrect fan-in occurs, a source reference is unavailable at that position, the supplied order is invalid, or an output port names no available vertex. Otherwise:
- Allocate one fresh clean value bit for each non-input node .
- Process nodes in the supplied order. Leave a constant- bit untouched; apply to a constant- bit. For a NOT node with input wire , apply then . For an AND node with inputs , apply . For an OR node, apply , then , then . If a two-port node uses the same source identifier twice, first allocate a fresh clean scratch bit , copy the source into by CNOT, use the distinct physical wires as the gate inputs, and uncopy immediately after writing .
- For each output port , apply CNOT from its named input or value wire to target bit .
- Append the inverse of the entire node-evaluation list in reverse chronological order, including the temporary source-copy and uncopy instructions. Return the resulting finite gate list, with the input register unchanged and the target changed only by the stated XOR into .
The inverse-list operation is defined instruction by instruction: , CNOT, and Toffoli are each replaced by themselves, in reverse order. The Boolean graph is an explicit finite input; this procedure makes no uniform-generation, oracle, or Turing-time claim.
Fresh-target NOT and OR gadgets
Statement
Let be distinct source wires and let be a distinct target wire initialized to . The chronological sequence followed by writes into . The sequence , , writes into , since . Every source wire is unchanged.
Facts & Assumptions
Given: Distinct source and target wires and the stated Pauli-, CNOT, and Toffoli actions on the ordered computational basis. Verify the target values and preservation of controls.
The Pauli matrices: In the ordered computational basis, , which sends to by matrix multiplication.
CNOT and Control-Target Order: In the ordered two-qubit basis, .
Denotational semantics of a finite layered circuit: A chronological list of layers , with applied first, denotes .
X, CNOT, Toffoli, and Fredkin are involutions: , CNOT, and Toffoli are unitary gates on their ordered registers.
Proof
Starting with , sets it to and the following CNOT changes it to . Both gates target only , so is unchanged; [F5] supplies their gate unitarity.
For the second sequence, the final target is . For these values are , respectively, which are exactly . The two CNOTs and Toffoli have controls only on , so neither source changes; [F5] supplies their gate unitarity.
Toffoli computes into a clean target and uncomputes it
Statement
Let be the values on two distinct control wires, let be a distinct clean target wire with value , and let be another distinct target wire with arbitrary value. Toffoli changes to while preserving the controls. Copying that value into by CNOT and applying Toffoli again, in the written chronological order, sends
The same operator identity holds on superpositions.
Facts & Assumptions
Given: The Toffoli action, a zero-initialized workspace bit, and a distinct arbitrary target bit. Prove the stated compute-copy-uncompute identity.
Toffoli and Fredkin gates: Toffoli maps to .
X, CNOT, Toffoli, and Fredkin are involutions: Toffoli is its own inverse.
Clean and dirty ancillas: A clean ancilla is initialized in and the complete subroutine must return it exactly to .
CNOT and Control-Target Order: In the ordered two-qubit basis, .
Denotational semantics of a finite layered circuit: A chronological list of layers , with applied first, denotes .
Tensor products of finitely many linear maps: A tensor map extends its factor maps linearly and acts factorwise on each elementary tensor.
The computational basis is orthonormal: The one-qubit computational basis is an orthonormal basis for its declared inner product.
The product basis is orthonormal and tensor dimensions multiply: The ordered tensor product of finite orthonormal factor bases is an orthonormal basis of the register.
Proof
Since , Toffoli sets to . The four control cases give target values , respectively, and the controls are unchanged.
CNOT from this work bit to the disjoint target changes to and leaves otherwise unchanged. The final Toffoli toggles by the same , returning it to ; by [F2] it is the inverse compute gate. Thus each basis input has the stated output and clean work.
The vectors , as ranges over its eight values, form a basis of the input subspace with the work factor fixed to , by [F7]–[F8]. Every gate is linear, so the basis-vector identity in Step 2.1 extends to every superposition in that subspace. The tensor-map rule [F6] makes each gate act factorwise on the ordered wires, preserving the displayed register order.
Compute-copy-uncompute restores clean workspace
Statement
Let be a unitary circuit on input register and clean work register , with an available circuit for . Suppose that for every ,
where occupies a designated -bit subregister of and is any remaining work string. Copying into a distinct arbitrary target register by bitwise CNOT and then applying to maps
The identity holds coherently on superpositions and with any reference register.
Facts & Assumptions
Given: The stated basis action of , disjoint target register , and available inverse circuit. Prove that the work is restored.
Clean and dirty ancillas: Clean workspace is initialized to the all-zero vector and must be returned exactly to that factor.
Clean and dirty ancilla identities extend to references and mixed states: Clean identities extend to reference registers by tensoring with identity and to arbitrary matrices by linearity.
CNOT and Control-Target Order: In the ordered two-qubit basis, .
Tensor products of finitely many linear maps: The tensor map acts factorwise on elementary tensors and extends uniquely by linearity.
Denotational semantics of a finite layered circuit: Chronological layers , with applied first, denote the ordered product .
Reversing a circuit implements its inverse: If the inverses of all gates are explicitly available, reversing the chronological gate order and adjointing each gate implements .
Finite registers and their ordered computational bases: An -qubit register is the ordered tensor product of copies of , with the first wire most significant; the empty register is with basis .
Big-endian encoding of ordered bit strings: A bit string occupies the computational-basis slot given by its big-endian index.
Big-endian bit-string indices are bijective: Every length- bit string labels exactly one computational-basis vector.
The computational basis is orthonormal: The computational basis of each nonempty qubit register is orthonormal.
The product basis is orthonormal and tensor dimensions multiply: Ordered product bases of finite registers form a basis of their tensor product, including the empty-register case.
X, CNOT, Toffoli, and Fredkin are involutions: CNOT is a unitary gate on its ordered register.
Proof
On a basis input, the forward computation gives . Since is disjoint, bitwise CNOT from the designated subregister changes an arbitrary target to and leaves unchanged. The intermediate state is therefore , with together occupying ; [F12] supplies the CNOT gate unitarity.
Applying to returns to by the assumed forward basis action and [F6]. The inverse is supplied on by the Given clause, so the disjoint target is untouched and remains . This proves the displayed basis action and exact restoration of all work required by the clean-ancilla contract [F1].
By [F7]–[F11], the ordered basis vectors form a basis of the subspace with work fixed to zero. Step 2.1 therefore extends by linearity to every superposition in that subspace, with data action . This data map is an involutive permutation of its orthonormal computational basis, since applying it twice restores ; hence is unitary. The complete compute-copy-inverse operation thus satisfies the clean identity in [F1], and [F2] extends it to every finite reference register and matrix. The tensor-map and chronological-circuit conventions [F4]–[F5] preserve the ordered factors in these extensions.
Gate, workspace, and serial-depth costs of reversible embedding
Statement
Let , , and . Let a finite topologically ordered Boolean DAG have non-input nodes, including constants, and input-port uses counted with multiplicity. Its gates are NOT, AND, OR, and constants, with fan-in at most two, and it has ordered output ports computing . Under the fixed elementary alphabet in Finite circuit resource accounting, counting each occurrence of , CNOT, and Toffoli as one gate and one serial layer, Reversible embedding of a Boolean circuit returns a circuit on the ordered input, target, and work registers implementing
for every basis input and every target string . It uses at most elementary gate occurrences, at most clean work bits, and serial depth at most . The same operator action holds coherently on arbitrary superpositions and after adjoining any finite reference register.
Facts & Assumptions
Given: The finite Boolean DAG convention, the procedure in Reversible embedding of a Boolean circuit, and the gate actions in the local suppliers. Prove correctness, clean-work restoration, and the stated bounds.
Boolean circuits: basis, fan-in, size, and depth: A Boolean circuit has constants and , and NOT, AND, and OR gates; AND and OR have fan-in two, while NOT has fan-in one. Its size is its number of non-input gates.
Reversible embedding of a Boolean circuit: The procedure computes each gate into fresh zero work, copies the designated outputs into arbitrary targets, and reverses the node-evaluation list.
Fresh-target NOT and OR gadgets: The fresh-target sequences write for NOT and for OR without changing sources.
Toffoli computes into a clean target and uncomputes it: Toffoli computes into a clean target, and copying followed by the inverse Toffoli restores that target to zero.
Clean and dirty ancilla identities extend to references and mixed states: Clean workspace identities extend to arbitrary references and matrices.
X, CNOT, Toffoli, and Fredkin are involutions: , CNOT, and Toffoli are each their own inverse.
The Pauli matrices: The Pauli matrix sends to and to .
Ordered tensor registers, their inner product, and wire permutations: An ordered tensor register retains the displayed factor order, and its product basis is ordered lexicographically by factor-index tuples.
Big-endian encoding of ordered bit strings: The first bit is the most significant position in the computational-basis index.
Big-endian bit-string indices are bijective: Each length- bit string labels exactly one computational-basis vector of the -qubit register.
Denotational semantics of a finite layered circuit: A chronological list of layers , with applied first, denotes .
The product basis is orthonormal and tensor dimensions multiply: The ordered tensor-product computational basis is orthonormal, including the work-register factors.
Finite circuit resource accounting: Circuit size counts gate occurrences, depth counts explicit layers, and width counts all wires including workspace wires.
Proof
Let be the number of two-port nodes whose two ports name the same source. Each non-input node uses at most three evaluation gates: at most one for a constant, two for NOT, one for AND, and three for OR. Each repeated-source node adds one CNOT copy and one uncopy, so the forward pass uses at most gates. Since each such node accounts for two of the port uses, , and the forward bound is at most . It uses value bits and temporary bits.
The output ports are copied by CNOTs into distinct target bits. Reversing the complete node-evaluation list uses at most another gates. By [F6], each gate is its own inverse; reversing both order and gate sequence therefore implements the inverse computation and returns every value and temporary bit to zero. The total is at most gate occurrences. A serial execution assigns each occurrence its own explicit layer, so the depth has the same bound by [F13]; [F11] specifies the chronological operator product.
Use [F9]–[F10] to identify each ordered bit string with its unique basis vector. Induct along the supplied topological order. A constant- node leaves its zero bit unchanged and a constant- node uses [F8]; NOT and OR nodes receive the outputs in [F3], and AND nodes receive the output in [F4]. If a two-port node repeats a source value , its fresh scratch bit is set to by CNOT; the two distinct physical control wires then both hold , so AND gives and OR gives . The scratch is immediately uncomputed by the same CNOT. Thus every value bit equals its Boolean node value and all temporary bits are zero before the output copy. The output CNOTs produce ; reversing the node list then restores every work bit without touching the input or target registers, whose order is fixed by [F7]. Since applying twice returns , the target action is a permutation of the ordered basis and is unitary by [F12]; the compiled gate list is unitary by [F6] and [F11].
The basis identity in Step 3.1 extends by linearity to every input vector, so it is the clean-ancilla identity required by [F5]. The lemma then extends it to every finite reference register and every matrix, hence to density matrices. The construction uses only the supplied finite list; no choice principle is used.
Coherent XOR function oracle
Definition
Let and let be a total Boolean function on ordered bit strings. Its coherent XOR oracle is the linear extension of
on the ordered input and target computational basis, where XOR is componentwise. The declared access contract states how many invocations count as queries and whether a controlled invocation is supplied. A query to this declared black box is counted separately from elementary gate size, depth, and width.
If is supplied instead by an explicit Boolean circuit, implementing means compiling that circuit and paying its reversible elementary-gate and workspace costs; the function description alone is not a free query. For this XOR oracle, its inverse is the same map, as proved in A total Boolean XOR oracle is unitary and involutive ↗. Controlled access remains a separate capability unless the contract explicitly provides it.
Parallel depth of reversible Boolean embedding
Statement
For a finite Boolean DAG over constants, NOT, AND, and OR, with fan-in at most two, let be its number of non-input nodes, its number of input-port uses counted with multiplicity, and its number of ordered output ports. Let be the number of nonempty layers obtained by grouping each non-input node according to the maximum number of non-input vertices on a path ending at that node. Let be the maximum number of input-port occurrences from one source wire into gates in one such layer, with if there are no gate input ports. There is a layer-respecting reversible circuit implementing the same XOR embedding as Reversible embedding of a Boolean circuit with gate occurrences and work bits. Let
Its depth is at most
The bound permits coherent fan-out of computational-basis labels by CNOT trees and does not assert arbitrary-state cloning or constant-factor preservation of Boolean-DAG depth. For bounded fan-in, .
Facts & Assumptions
Given: The reversible embedding construction, finite gate/depth conventions, and disjoint ordered registers. Prove the scheduling and resource bound.
Gate, workspace, and serial-depth costs of reversible embedding: The compute-copy-reverse construction implements the XOR embedding and restores clean work.
Finite circuit resource accounting: Size counts gate occurrences, depth counts explicit layers, and width counts all wires including workspace wires.
Denotational semantics of a finite layered circuit: Chronological layers , with applied first, denote ; disjoint gates in a layer are interpreted as parallel.
Ordered tensor registers, their inner product, and wire permutations: An ordered tensor register retains the displayed factor order, and its product basis is ordered lexicographically by factor-index tuples.
Tensor products of finitely many linear maps: The tensor map of a finite family of linear maps acts on each elementary tensor by applying the corresponding map to each factor.
CNOT and Control-Target Order: In the ordered two-qubit basis, .
The Pauli matrices: The Pauli matrix flips a computational-basis bit.
Toffoli and Fredkin gates: Toffoli maps to and preserves its two controls.
Fresh-target NOT and OR gadgets: NOT and OR are computed into a distinct zero target by the stated two- and three-gate gadgets, with source wires preserved.
X, CNOT, Toffoli, and Fredkin are involutions: , CNOT, and Toffoli are each their own inverse and unitary on their ordered registers.
The computational basis is orthonormal: Each one-qubit computational basis is an orthonormal basis for its declared inner product.
The product basis is orthonormal and tensor dimensions multiply: Ordered tensor products of finite orthonormal factor bases form an orthonormal basis, including empty registers.
Big-endian encoding of ordered bit strings: Ordered bit strings label computational-basis slots by their big-endian indices.
Big-endian bit-string indices are bijective: Every length- bit string labels exactly one computational-basis vector, including the empty string.
Proof
For a source wire used times in one DAG layer, start with that wire as one leaf and in each round apply CNOT from each current leaf to at most one fresh zero target. After rounds there are at least distinct leaves, so at most rounds suffice. The tree needs CNOTs, and summing over source wires and layers gives at most copies. By [F4], each leaf carries the source's basis value and each CNOT leaves its control unchanged. The rounds are successive explicit layers in the order specified by [F9], counted by [F10].
Fix a DAG layer and suppose each source wire at its start holds its Boolean circuit value. Fan out every source to private leaves by Step 1.1. Each non-input node has a distinct fresh zero value bit. A constant- node leaves that bit unchanged, and a constant- node flips it by [F5]. For NOT, the two sublayers in [F7] write ; for AND, [F6] writes ; for OR, [F7] writes . Repeated logical sources have distinct physical leaves, and every gate preserves its leaves. Targets are distinct between nodes, so each of these at most three gate sublayers has disjoint supports. Reversing the fan-out trees restores all private leaves to zero, since the evaluation gates did not change them; [F8] supplies the inverse CNOTs. By [F9] these are chronological sublayers, and [F10] counts them. The layer therefore takes at most depth.
If a non-input node feeds a node , every longest path ending at extends by that edge, so the layer index of is strictly smaller than the layer index of . Induct on the layer index. At the first layer all non-input predecessors are absent; at a later layer every non-input predecessor has its correct value by induction. Step 2.1 then writes the Boolean value of each node in the current layer and clears its temporary leaves. Thus after all layers every value bit equals its node's Boolean evaluation, including when two ports use the same source, and all fan-out leaves are zero.
For each output source selected times, use Step 1.1 to produce private leaves in at most rounds. Copy each leaf into its distinct target bit in one layer, then reverse the tree in at most rounds. Summing over output sources gives at most temporary targets, and the output stage has depth at most . This also covers repeated output ports and output sources that are input wires. The chronological composition is the one in [F9], and [F10] counts the explicit layers.
Copy each output into its target, then reverse the layer computations. In reverse order the fan-out tree is first recreated, the node gates are inverted to clear their value bits, and the fan-out tree is then undone; [F8] makes these same CNOT, X, and Toffoli gates available as inverses. This costs at most another depth and returns every value bit and temporary copy to zero. Adding this reverse depth, the output stage from Step 4.1, and the forward depth from Steps 2.1–3.1 gives . There are value bits, at most temporary input-copy bits, and at most output-copy bits, for work. The input-copy trees and their reversals in both computation passes use at most CNOTs, and the output-copy trees and their reversals use at most CNOTs, output copying uses CNOTs, and Boolean evaluation and reversal use at most gates, hence the total is . Since fan-in is at most two, . By Step 3.1 each output source holds its Boolean value, so Step 4.1 changes the target to ; reversing node computations restores the work without changing the input or target. This is the XOR embedding specified by [F1]. By [F11]–[F14], ordered bit strings identify the complete computational basis of the input, target, and work registers, including the zero-qubit case; the basis identity therefore extends by linearity to superpositions. The finite circuit denotes the chronological operator product [F9], its resource coordinates are counted by [F10], and fan-out CNOTs may entangle copies during computation, but reversing them restores each copy bit to zero, so no arbitrary unknown state is cloned.
A total Boolean XOR oracle is unitary and involutive
Statement
For every total Boolean function , including noninjective functions, the coherent XOR oracle is unitary and satisfies . Hence .
Facts & Assumptions
Given: The basis action in Coherent XOR function oracle on the finite ordered computational basis. Prove involutivity and unitarity without assuming injective.
Coherent XOR function oracle: for every ordered input and target string.
Big-endian encoding of ordered bit strings: The big-endian index is , and the word occupies the basis slot numbered by that index.
Finite registers and their ordered computational bases: The -qubit register is the ordered tensor product of copies of , with tuples in lexicographic order and the first wire most significant; for it is with basis .
The computational basis is orthonormal: The ordered computational basis of each register is an orthonormal basis for its declared inner product.
Big-endian bit-string indices are bijective: For every , is a bijection from to .
The product basis is orthonormal and tensor dimensions multiply: The lexicographically ordered elementary tensors of the factor bases form an orthonormal basis of the tensor register.
Proof
Apply twice to a basis vector. The first application gives ; the second gives because every bit added modulo two twice is zero. The input is preserved throughout, so injectivity of is not needed.
By [F2]–[F6], the input and target strings label the entire finite orthonormal product basis in the declared order. Step 1.1 shows that the oracle map is a permutation of this basis, so its matrix has orthonormal columns and satisfies . Therefore it is unitary, and Step 1.1 gives its inverse as itself.
Phase kickback from an XOR oracle
Statement
Let be total, let , and define the normalized character target
where is the dot product modulo two. Then
For a one-bit output with , . Thus the phase action is obtained with one invocation of the declared XOR oracle, with target preparation cost accounted separately.
Facts & Assumptions
Given: The coherent XOR action and ordered bit-string basis. Prove the character-target identity.
A total Boolean XOR oracle is unitary and involutive: The XOR oracle is a unitary involution for every total Boolean function.
Finite registers and their ordered computational bases: The -qubit register is the ordered tensor product of copies of , with tuples in lexicographic order and the first wire most significant; the empty register is .
The computational basis is orthonormal: The ordered computational basis of each register is an orthonormal basis for its declared inner product.
Big-endian bit-string indices are bijective: For every , the big-endian encoding is a bijection from the length- bit strings to the basis indices.
The product basis is orthonormal and tensor dimensions multiply: Ordered product basis vectors form an orthonormal basis of the tensor register.
Exact one-qubit gates and rotations: The exact Hadamard matrix is .
Proof
By [F4]–[F6], the target basis vectors are orthonormal and the encoding lists each exactly once; hence has squared norm . Applying the oracle termwise gives . Set . Then and , so the sum is .
By [F3]–[F6], the ordered input basis spans its register, so linearity gives the same phase action on every superposition , with the target factor unchanged. When and , multiplying the matrix in [F7] by gives . Also , so this is a unitary target preparation. The unitary character of the oracle is supplied by [F2].
Oracle phase queries and compiled gate costs are distinct
Statement
An invocation counts as one oracle query only under an explicit oracle-access contract. A declared phase oracle therefore costs one phase query per invocation. A declared XOR oracle for a Boolean function also implements its phase action in one XOR-oracle query by using target , with the cost of preparing that target stated separately. If is instead given by an explicit Boolean circuit, constructing its XOR or phase action incurs the compiled gate, depth, and workspace costs of Gate, workspace, and serial-depth costs of reversible embedding; it is not a free query. Controlled black-box access must be declared or constructed with its own cost. The XOR oracle is self-inverse, but an invocation used to apply that inverse still counts as one query.
Facts & Assumptions
Given: The explicit query-counting convention, the XOR-oracle contract, the phase-kickback identity, and the reversible compiler's gate bounds. Establish the query/gate distinction.
Coherent XOR function oracle: Query count belongs to a declared black-box XOR-oracle contract; an explicit circuit implementation is a compiled gate list.
Phase kickback from an XOR oracle: A Boolean XOR oracle applies the phase with target in one oracle invocation and returns that target unchanged.
Gate, workspace, and serial-depth costs of reversible embedding: An explicit Boolean circuit can be compiled to a clean XOR embedding with its gate, depth, and work costs charged.
A total Boolean XOR oracle is unitary and involutive: The XOR oracle is its own inverse.
Controlled Unitary Access: Controlled access means the chosen operation model explicitly grants the block operator ; an ordinary black-box call to does not grant it implicitly.
Finite circuit resource accounting: The operation model records query costs separately from gate occurrences, depth layers, and classical bit costs.
Proof
A phase oracle for a Boolean function means the diagonal map , and a declared query contract counts each invocation of its named black box as one query. Thus a declared phase-oracle invocation is one phase query. If the supplied black box is instead the XOR map, [F2] gives the same phase action using exactly one XOR-oracle invocation; target-state preparation is a separate ordinary circuit operation, charged in the separate coordinates of [F6].
If the only input for is an explicit Boolean circuit, [F3] replaces each required function evaluation by its finite compiled gate list, so the listed gates, depth, and work are charged under the separate resource coordinates [F6]. There is no black-box invocation to count unless the contract separately supplies one. Likewise a controlled black-box call requires declared controlled access [F5]; and although by [F4], each call made to apply it remains one query invocation.
5 · Examples, counterexamples and false statements
None yet.