How statement and proof provenance work
The first chip identifies the source of the statement or construction; the second identifies the source of its local proof or verification.
- Literature-sourced: the exact statement appears in a cited source; only wording and notation differ.
- AI-adapted: a semantically identical restatement of literature-sourced material, modulo indexing, notation, and boundary cases adopted by the library.
- AI-generated: a genuinely novel statement formulated by AI, with no source for the claim itself.
These labels describe origin, not correctness: citations and verification chips remain separate evidence.
Boolean Circuits and Nonuniform Complexity
1 · Prerequisites
- Construction of the Natural Numbers
- Construction of the Real Numbers via Cauchy Sequences
- Construction of the Real Numbers via Dedekind Cuts
- Countability and Uncountability
- Decidable, Recognizable, and Enumerable Languages
- Diagonalization and the Halting Problem
- Finite Counting, Factorials and Binomial Coefficients
- Formal Languages, Encodings, and Decision Problems
- Foundations of the Real Numbers for Analysis
- Linear Recurrences and Rational Generating Functions
- Logarithmic Space, NL, and Reachability
- P, NP, coNP, and Polynomial Reductions
- Relations, Functions, and Quotients
- Resource Bounds and Machine Invariance
- Robust Machine Models and Universal Computation
- Roots, Rational Powers, and Classical Inequalities
- Sequences and Limits
- The ZFC Axioms and the Basic Set Constructions
- Time and Space Hierarchy Theorems
- Turing Machines, Configurations, and Computation
2 · Summary
This draft page develops the assigned conventions and keeps every resource, type, and quantifier explicit.
3 · Logical flowchart
4 · Definitions, theorems and proofs
Boolean circuits: basis, fan-in, size, and depth
Definition
A Boolean circuit on inputs is a finite directed acyclic graph with inputs , constants and , and NOT, AND, and OR gates; AND and OR have fan-in two, while NOT has fan-in one. One node is designated as the output. The circuit's value is the value at that node after evaluating the graph in topological order. Its size is its number of non-input gates, and its depth is the largest number of non-input gates on a directed path ending at the output (a path may begin at an input or a constant).
If two fixed finite bounded-arity bases can simulate every gate (and every constant) of one another by fixed finite circuits, then changing between them costs only constant factors in size and depth. In particular this holds for any two such functionally complete bases with simulable constants. No such claim is made for an arbitrary finite basis that may fail to express one of the Boolean operations.
Circuit families and P/poly
Definition
A circuit family is a sequence (C_n) with exactly n inputs at length n. It recognizes L if C_n(x)=1 exactly when x belongs to L for every n-bit x. P/poly contains exactly the languages recognized by families with polynomial size; no algorithm that constructs C_n from n is required.
Every polynomial-time language has polynomial-size circuits
Statement
Every polynomial-time language belongs to .
Facts & Assumptions
Given: a language and a deterministic machine deciding in time for a polynomial .
Membership in supplies such a polynomial-time decider, by The class P.
A polynomial-size family, with one circuit chosen separately at each length, recognizes a language in , by Circuit families and P/poly.
Fixed mutually simulable Boolean bases differ by only constant factors in size and depth, by Boolean circuits: basis, fan-in, size, and depth.
Proof
Fix an input length . Encode a configuration of by the state, head position, and the tape cells that can be visited in steps. Each bit of the next configuration depends on only a constant-size neighbourhood of the current configuration, so it is computed by a constant-size Boolean subcircuit. Pad halting configurations so that this update is defined through time .
Wire copies of the update layer in sequence, initialize the first layer from the input bits, and read the accepting-state bit in the final layer. There are encoded bits per layer and layers, so the resulting circuit has gates. Replacing its fixed local basis by the page basis changes this bound only by a constant factor.
For every , exactly when accepts . Thus is a polynomial-size family recognizing , as required by [L2]. The construction proves existence of each and does not assert a uniform generator.
Polynomial advice for a deterministic machine
Definition
An advised polynomial-time machine consists of a deterministic polynomial-time machine M and strings a_n of polynomial length. On each n-bit input x it receives (x,a_n), and accepts exactly the intended language. The string is length-indexed and need not be computable from n.
P/poly equals polynomial time with polynomial advice
Statement
is exactly the class of languages decided in polynomial time with polynomial-length advice.
Facts & Assumptions
Given: the circuit-family and advised-machine conventions of the claim.
A language has a polynomial-size circuit at each input length , by Circuit families and P/poly.
Advice may depend on the input length and need not be computable, but has polynomial length, by Polynomial advice for a deterministic machine.
Every polynomial-time language has polynomial-size circuits, by Every polynomial-time language has polynomial-size circuits.
Proof
Suppose has size at most . Encode as a topologically ordered gate list: each of its at most records contains a constant-size gate tag and at most two indices of bits. This is polynomial advice. A fixed evaluator scans the list in topological order and computes in polynomial time, so [L2] gives an advised decider.
Conversely, let run in polynomial time with . Use a fixed self-delimiting encoding whose length depends only on and , and let . This is a language in , so [L3] supplies polynomial-size circuits for . For a fixed , put and take the circuit for the common encoding length of with . Hardwire the delimiter bits and all bits of , leaving only the bits of free. Because , the resulting -input circuit has polynomial size and agrees with the original computation ; no change to the advice string or its length is made.
Step 1.1 proves the circuit-to-advice inclusion and step 1.2 proves the advice-to-circuit inclusion, including the advice-length and simulation-size bounds.
Some undecidable languages have polynomial-size circuits
Statement
There is an undecidable language in ; indeed, one can choose a language having constant-size circuits at every input length.
Facts & Assumptions
Given: a fixed effective enumeration of Turing machines.
The diagonal halting problem is undecidable, by The halting problem is recognizable and undecidable.
A family need not be effectively constructible from its input length, by Circuit families and P/poly.
Proof
Let and form the tally language . A decider for would decide by mapping to , so is undecidable by [L1]. Define the binary length language . If were decidable, its decider restricted to would decide ; hence is undecidable.
For each , choose to be the constant-one circuit if , and the constant-zero circuit otherwise. Then for every , exactly when . The circuits have constant size, and their non-effective length-by-length choice is permitted by [L2].
Thus is both undecidable and recognized by a polynomial-size circuit family.
Boolean formulas and deterministic branching programs
Definition
A Boolean formula is a finite rooted tree whose leaves are labelled by input variables or constants , and whose internal nodes are NOT gates with one child or AND/OR gates with two children. The root is the output, and evaluation proceeds from leaves to root. A variable or constant may label several distinct leaves; all occurrences of a variable receive the same input value. Thus computed subformulas are not shared, but input variables may be used repeatedly. In the gate-count convention of Boolean circuits: basis, fan-in, size, and depth, its size counts connective gates and constant occurrences, but not variable leaves.
A deterministic branching program is a finite acyclic query graph with a start node and sinks labelled or . Each internal node is labelled by an input bit and has one outgoing edge labelled and one outgoing edge labelled ; computation follows the edge whose label is the queried bit's value. Its size is its number of vertices. These are distinct size models.
AC0, NC1, and NC under a stated uniformity convention
Definition
All families in this definition are logspace-uniform. For bounded-fan-in families this means exactly the query interface of A logspace-uniform Boolean circuit family. For an unbounded-fan-in gate, the same interface is extended by a fan-in query and by predecessor queries that return the -th predecessor of gate (or report that is out of range); the transducer must answer all such queries in logarithmic space.
has polynomial size, constant depth, unbounded-fan-in AND/OR, and NOT gates. has polynomial size, bounded fan-in, and logarithmic depth. is the union of polynomial-size bounded-fan-in families of polylogarithmic depth. This convention does not constrain arbitrary families.
NC1 is contained in L, and L is contained in NC2
Statement
under the page's logspace-uniform circuit convention.
Facts & Assumptions
Given: the uniform circuit and read-only-input machine conventions.
An family has polynomial size, bounded fan-in, logarithmic depth, and logspace uniformity, by AC0, NC1, and NC under a stated uniformity convention.
consists of languages decided with deterministic logarithmic workspace, by The classes L and NL.
Proof
Let have depth . Evaluate its output by a depth-first walk. Store the current root-to-gate child-choice word (at most bits), a constant amount of traversal state per current level encoded in that word, and counters. Whenever a gate address is needed, recompute it from the output by replaying the stored choices, using logspace uniformity to obtain each gate record. This uses space; bounded fan-in lets the walk combine the child values. Thus .
Let be a logspace decider. On inputs of length it has polynomially many configurations, each indexed with bits, and its start, accepting, and one-step adjacency predicates are logspace uniform. Boolean matrix squaring computes paths of length at most from those predicates. There are squarings, and each Boolean matrix product has bounded-fan-in depth and polynomial size, so start-to-accept reachability has depth and polynomial size. The gate indices and wiring are generated in logspace from . Hence .
The two simulations prove both stated containments without storing a logarithmic stack of logarithmic-size gate addresses.
Counting bounded-size Boolean circuits
Statement
For , the number of Boolean functions on inputs computed by circuits of size at most over the fixed page basis is at most
Facts & Assumptions
Given: integers .
The circuit basis is fixed and has arity at most two, by Boolean circuits: basis, fan-in, size, and depth.
Independent finite choices multiply, by The product rule: , and .
Proof
A topologically numbered gate has at most a fixed number of type choices and at most two input-wire indices among at most available wires. Thus each gate record has at most possibilities; choosing an output wire adds at most possibilities.
By [L2], circuits with exactly gates therefore number at most . Summing over gives at most because .
Distinct encodings may compute the same function, so this circuit count is also an upper bound on the number of represented Boolean functions.
Almost all Boolean functions require exponential circuit size
Statement
As , the proportion of Boolean functions on variables having circuit size at most tends to . In particular, almost all Boolean functions require circuit size .
Facts & Assumptions
Given: the fixed circuit basis of the page.
Size-at-most- circuits represent at most functions, with the explicit gate-record count in the proof, by Counting bounded-size Boolean circuits.
There are Boolean functions on inputs, by The set of functions between finite sets is finite, with .
Proof
Put and let be the fixed number of available gate types. The explicit encoding in [L1] gives at most circuits. Since is constant, for all sufficiently large the base-two logarithm is at most .
Dividing the resulting bound by the total from [L2] gives at most , which tends to . Hence a uniformly random truth table has size greater than with probability tending to .
This is an existence-and-density argument over truth tables; it does not select or compute an explicit hard family.
Circuit satisfiability
Definition
CircuitSAT consists of well-formed finite topologically numbered Boolean gate lists with a designated output for which some input assignment makes that output one; malformed lists are rejected.
CircuitSAT is NP-complete
Statement
is NP-complete under polynomial-time many-one reductions.
Facts & Assumptions
Given: the gate-list encoding of .
Well-formed gate lists have a designated output, and malformed lists are rejected, by Circuit satisfiability.
is NP-complete, by SAT is NP-complete.
A polynomial-time many-one reduction must preserve membership in both directions, by Polynomial-time many-one reductions.
NP-completeness means membership in NP together with NP-hardness, by NP-hard and NP-complete languages.
Proof
A verifier first rejects a malformed list. Otherwise it guesses one bit for every input gate, evaluates the gates in topological order, and accepts iff the designated output is . Its time is polynomial in the list length, so .
Given a Boolean formula , create one circuit input for each variable and one circuit gate for each connective, ordered from leaves toward the root; designate the root gate as output. This map is polynomial time and produces a circuit satisfying for every assignment . Therefore iff , so [L2] and [L3] give NP-hardness.
Combining membership from step 1.1 with hardness from step 1.2 proves NP-completeness by [L4].
The Karp--Lipton collapse
Statement
If , then the polynomial hierarchy collapses to its second level: Here consists of languages expressible as for a polynomial-time predicate and polynomially bounded strings; reverses the two quantifiers, and is the union of the constant-alternation levels.
Facts & Assumptions
Given: .
permits one polynomial-size circuit independently at each input length, by Circuit families and P/poly.
Proof
Let be any polynomial-time predicate with polynomially bounded , and form the NP language By the hypothesis, has polynomial-size decision circuits. Successively querying whether the current prefix has a satisfying extension, first with a appended and then with a appended, composes polynomially many copies of these decision circuits into a polynomial-size search circuit. On input for which some witness exists, it outputs an actual satisfying .
Let , so . For each fixed input length, step 1.1 supplies a single polynomial-size search circuit which works for every pair of the relevant padded lengths. Therefore If , choose the search circuit from step 1.1; conversely, any circuit satisfying the right side supplies the required witness for every . The predicate merely evaluates and checks , so it is polynomial-time and the right side is a formula.
Thus ; the reverse containment after complementing gives equality of the second levels. Replacing each inner block of a higher alternating formula by its form and merging adjacent existential and universal blocks inductively collapses every constant-alternation level to . Consequently .
5 · Examples, counterexamples and false statements
Polynomial-size circuits imply a uniform polynomial-time generator
Statement
Every polynomial-size circuit family has a polynomial-time algorithm that, given , outputs its length- circuit.
Facts & Assumptions
Given: the nonuniform family convention.
requires only a separate polynomial-size circuit at each length and no generator, by Circuit families and P/poly.
There is an undecidable language recognized by constant-size circuits, by Some undecidable languages have polynomial-size circuits.
Refutation
Let be the constant-size family for the undecidable length language from [L2]. If a polynomial-time generator output on input , then on any word one could compute and evaluate that constant- size circuit on in polynomial time.
The resulting algorithm would decide the language, contradicting its undecidability. Hence this polynomial-size family has no such generator.
The size condition in [L1] is therefore strictly nonuniform; effective generation is an additional hypothesis.
Shannon counting gives an efficiently explicit circuit-hard function
Statement
The Shannon counting argument itself gives a polynomial-time computable family of Boolean functions having exponential circuit complexity.
Facts & Assumptions
Given: the Shannon counting argument.
Counting circuits gives only an upper bound on how many truth tables they represent, by Counting bounded-size Boolean circuits.
The resulting theorem says that almost all truth tables are hard, by Almost all Boolean functions require exponential circuit size.
Refutation
The argument in [L1] and [L2] compares two cardinalities and concludes that the complement of the set of small-circuit truth tables is nonempty (and large). One can make an ineffective-for-complexity selection computable by enumerating every bounded-size circuit, forming all of their truth tables, and choosing the lexicographically first missing table. That exhaustive procedure, however, takes time exponential (indeed much larger) in the truth-table length and supplies no polynomial-time algorithm for evaluating the selected function on an input.
Consequently the counting proof establishes existential hardness and even permits a brute-force computable choice, but it does not by itself produce an efficiently explicit hard family. Such a family requires an additional efficient construction and lower-bound argument absent from the count.
This distinction refutes the claim that the Shannon counting argument itself supplies a polynomial-time computable hard family.