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The first chip identifies the source of the statement or construction; the second identifies the source of its local proof or verification.

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10 results · all verified · 6 also independently AI-judged
Every result on this page is machine-checked by a proof checker and read in full and owner-audited; the judge is an additional, independent cross-model AI review of the proofs. The 4 not AI-judged were verified by owner audit (typically over a confirmed judge false positive), not failures.

Boolean Circuits and Nonuniform Complexity

1 · Prerequisites

2 · Summary

This draft page develops the assigned conventions and keeps every resource, type, and quantifier explicit.

3 · Logical flowchart

4 · Definitions, theorems and proofs

DefinitionDefinition: Literature-sourcedProof: Not applicablejudge pass (gpt-5.6-terra)audited 2026-09-07Open item page →

Boolean circuits: basis, fan-in, size, and depth

Definition

A Boolean circuit on n inputs is a finite directed acyclic graph with inputs x1,,xn, constants 0 and 1, and NOT, AND, and OR gates; AND and OR have fan-in two, while NOT has fan-in one. One node is designated as the output. The circuit's value is the value at that node after evaluating the graph in topological order. Its size is its number of non-input gates, and its depth is the largest number of non-input gates on a directed path ending at the output (a path may begin at an input or a constant).

If two fixed finite bounded-arity bases can simulate every gate (and every constant) of one another by fixed finite circuits, then changing between them costs only constant factors in size and depth. In particular this holds for any two such functionally complete bases with simulable constants. No such claim is made for an arbitrary finite basis that may fail to express one of the Boolean operations.

DefinitionDefinition: Literature-sourcedProof: Not applicablejudge pass (gpt-5.6-terra)audited 2026-09-07Open item page →

Circuit families and P/poly

Definition

A circuit family is a sequence (C_n) with exactly n inputs at length n. It recognizes L if C_n(x)=1 exactly when x belongs to L for every n-bit x. P/poly contains exactly the languages recognized by families with polynomial size; no algorithm that constructs C_n from n is required.

TheoremStatement: Literature-sourcedProof: AI-generatedprecheck passjudge pass (gpt-5.6-terra)audited 2026-09-07Open item page →

Every polynomial-time language has polynomial-size circuits

Statement

Every polynomial-time language belongs to P/poly.

Facts & Assumptions

Given: a language LP and a deterministic machine M deciding L in time p(n) for a polynomial p.

[L1]

Membership in P supplies such a polynomial-time decider, by The class P.

[L2]

A polynomial-size family, with one circuit chosen separately at each length, recognizes a language in P/poly, by Circuit families and P/poly.

[L3]

Fixed mutually simulable Boolean bases differ by only constant factors in size and depth, by Boolean circuits: basis, fan-in, size, and depth.

Proof

technique · direct
1.1

Fix an input length n. Encode a configuration of M by the state, head position, and the O(p(n)) tape cells that can be visited in p(n) steps. Each bit of the next configuration depends on only a constant-size neighbourhood of the current configuration, so it is computed by a constant-size Boolean subcircuit. Pad halting configurations so that this update is defined through time p(n).

L1givenconstruct
2.1

Wire p(n) copies of the update layer in sequence, initialize the first layer from the n input bits, and read the accepting-state bit in the final layer. There are O(p(n)) encoded bits per layer and p(n) layers, so the resulting circuit Cn has O(p(n)2) gates. Replacing its fixed local basis by the page basis changes this bound only by a constant factor.

L3step 1.1
3.1

For every x{0,1}n, Cn(x)=1 exactly when M accepts x. Thus (Cn) is a polynomial-size family recognizing L, as required by [L2]. The construction proves existence of each Cn and does not assert a uniform generator.

L2step 2.1
DefinitionDefinition: Literature-sourcedProof: Not applicablejudge pass (gpt-5.6-terra)audited 2026-09-07Open item page →

Polynomial advice for a deterministic machine

Definition

An advised polynomial-time machine consists of a deterministic polynomial-time machine M and strings a_n of polynomial length. On each n-bit input x it receives (x,a_n), and accepts exactly the intended language. The string is length-indexed and need not be computable from n.

TheoremStatement: Literature-sourcedProof: AI-generatedprecheck passjudge pass (gpt-5.6-terra)audited 2026-09-07Open item page →

P/poly equals polynomial time with polynomial advice

Statement

P/poly is exactly the class of languages decided in polynomial time with polynomial-length advice.

Facts & Assumptions

Given: the circuit-family and advised-machine conventions of the claim.

[L1]

A P/poly language has a polynomial-size circuit Cn at each input length n, by Circuit families and P/poly.

[L2]

Advice may depend on the input length and need not be computable, but has polynomial length, by Polynomial advice for a deterministic machine.

[L3]

Every polynomial-time language has polynomial-size circuits, by Every polynomial-time language has polynomial-size circuits.

Proof

technique · direct
1.1

Suppose (Cn) has size at most p(n). Encode Cn as a topologically ordered gate list: each of its at most p(n) records contains a constant-size gate tag and at most two indices of O(log(n+p(n))) bits. This is polynomial advice. A fixed evaluator scans the list in topological order and computes Cn(x) in polynomial time, so [L2] gives an advised decider.

L1L2given
1.2

Conversely, let M(x,an) run in polynomial time with anp(n). Use a fixed self-delimiting encoding x,a whose length depends only on x and a, and let B={x,a:M(x,a)=1}. This is a language in P, so [L3] supplies polynomial-size circuits for B. For a fixed n, put mn=an and take the circuit for the common encoding length of x,an with x=n. Hardwire the delimiter bits and all bits of an, leaving only the n bits of x free. Because mnp(n), the resulting n-input circuit has polynomial size and agrees with the original computation M(x,an); no change to the advice string or its length is made.

L2L3givenconstruct
2.1

Step 1.1 proves the circuit-to-advice inclusion and step 1.2 proves the advice-to-circuit inclusion, including the advice-length and simulation-size bounds.

step 1.1step 1.2
TheoremStatement: Literature-sourcedProof: AI-generatedprecheck passjudge pass (gpt-5.6-terra)audited 2026-09-07Open item page →

Some undecidable languages have polynomial-size circuits

Statement

There is an undecidable language in P/poly; indeed, one can choose a language having constant-size circuits at every input length.

Facts & Assumptions

Given: a fixed effective enumeration (Mn)nN of Turing machines.

[L1]

The diagonal halting problem is undecidable, by The halting problem is recognizable and undecidable.

[L2]

A P/poly family need not be effectively constructible from its input length, by Circuit families and P/poly.

Proof

technique · direct
1.1

Let H={n:Mn(n) halts} and form the tally language U={1n:nH}. A decider for U would decide H by mapping n to 1n, so U is undecidable by [L1]. Define the binary length language L={x:1xU}. If L were decidable, its decider restricted to 1n would decide U; hence L is undecidable.

L1givenconstruct
2.1

For each n, choose Cn to be the constant-one circuit if 1nU, and the constant-zero circuit otherwise. Then for every x{0,1}n, Cn(x)=1 exactly when xL. The circuits have constant size, and their non-effective length-by-length choice is permitted by [L2].

L2step 1.1construct
3.1

Thus L is both undecidable and recognized by a polynomial-size circuit family.

step 1.1step 2.1
DefinitionDefinition: Literature-sourcedProof: Not applicableaudited 2026-09-07Open item page →

Boolean formulas and deterministic branching programs

Definition

A Boolean formula is a finite rooted tree whose leaves are labelled by input variables or constants 0,1, and whose internal nodes are NOT gates with one child or AND/OR gates with two children. The root is the output, and evaluation proceeds from leaves to root. A variable or constant may label several distinct leaves; all occurrences of a variable receive the same input value. Thus computed subformulas are not shared, but input variables may be used repeatedly. In the gate-count convention of Boolean circuits: basis, fan-in, size, and depth, its size counts connective gates and constant occurrences, but not variable leaves.

A deterministic branching program is a finite acyclic query graph with a start node and sinks labelled 0 or 1. Each internal node is labelled by an input bit and has one outgoing edge labelled 0 and one outgoing edge labelled 1; computation follows the edge whose label is the queried bit's value. Its size is its number of vertices. These are distinct size models.

DefinitionDefinition: Literature-sourcedProof: Not applicablejudge pass (gpt-5.6-terra)audited 2026-09-07Open item page →

AC0, NC1, and NC under a stated uniformity convention

Definition

All families in this definition are logspace-uniform. For bounded-fan-in families this means exactly the query interface of A logspace-uniform Boolean circuit family. For an unbounded-fan-in gate, the same interface is extended by a fan-in query and by predecessor queries (v,j) that return the j-th predecessor of gate v (or report that j is out of range); the transducer must answer all such queries in logarithmic space.

AC0 has polynomial size, constant depth, unbounded-fan-in AND/OR, and NOT gates. NC1 has polynomial size, bounded fan-in, and logarithmic depth. NC is the union of polynomial-size bounded-fan-in families of polylogarithmic depth. This convention does not constrain arbitrary P/poly families.

PropositionStatement: Literature-sourcedProof: AI-generatedprecheck passjudge pass (gpt-5.6-terra)audited 2026-09-07Open item page →

NC1 is contained in L, and L is contained in NC2

Statement

NC1LNC2 under the page's logspace-uniform circuit convention.

Facts & Assumptions

Given: the uniform circuit and read-only-input machine conventions.

[L1]

An NC1 family has polynomial size, bounded fan-in, logarithmic depth, and logspace uniformity, by AC0, NC1, and NC under a stated uniformity convention.

[L2]

L consists of languages decided with deterministic logarithmic workspace, by The classes L and NL.

Proof

technique · direct
1.1

Let Cn have depth d=O(logn). Evaluate its output by a depth-first walk. Store the current root-to-gate child-choice word (at most d bits), a constant amount of traversal state per current level encoded in that word, and O(logn) counters. Whenever a gate address is needed, recompute it from the output by replaying the stored choices, using logspace uniformity to obtain each gate record. This uses O(logn) space; bounded fan-in lets the walk combine the child values. Thus NC1L.

L1L2given
1.2

Let M be a logspace decider. On inputs of length n it has polynomially many configurations, each indexed with O(logn) bits, and its start, accepting, and one-step adjacency predicates are logspace uniform. Boolean matrix squaring computes paths of length at most 2i from those predicates. There are O(logn) squarings, and each Boolean matrix product has bounded-fan-in depth O(logn) and polynomial size, so start-to-accept reachability has depth O(log2n) and polynomial size. The gate indices and wiring are generated in logspace from (n,i,u,v). Hence LNC2.

L1L2givenconstruct
2.1

The two simulations prove both stated containments without storing a logarithmic stack of logarithmic-size gate addresses.

step 1.1step 1.2
LemmaStatement: Literature-sourcedProof: AI-generatedprecheck passaudited 2026-09-07Open item page →

Counting bounded-size Boolean circuits

Statement

For n,s1, the number of Boolean functions on n inputs computed by circuits of size at most s over the fixed page basis is at most 2O(slog(n+s)).

Facts & Assumptions

Given: integers n,s1.

[L1]

The circuit basis is fixed and has arity at most two, by Boolean circuits: basis, fan-in, size, and depth.

Proof

technique · direct
1.1

A topologically numbered gate has at most a fixed number b of type choices and at most two input-wire indices among at most n+s available wires. Thus each gate record has at most b(n+s)2 possibilities; choosing an output wire adds at most n+s possibilities.

L1given
2.1

By [L2], circuits with exactly rs gates therefore number at most (n+s)[b(n+s)2]r. Summing over 0rs gives at most (s+1)(n+s)[b(n+s)2]s=2O(slog(n+s)) because s1.

L2step 1.1algebra
3.1

Distinct encodings may compute the same function, so this circuit count is also an upper bound on the number of represented Boolean functions.

step 2.1
TheoremStatement: Literature-sourcedProof: AI-generatedprecheck passaudited 2026-09-07Open item page →

Almost all Boolean functions require exponential circuit size

Statement

As n, the proportion of Boolean functions on n variables having circuit size at most 2n/(10n) tends to 0. In particular, almost all Boolean functions require circuit size Ω(2n/n).

Facts & Assumptions

Given: the fixed circuit basis of the page.

[L1]

Size-at-most-s circuits represent at most 2O(slog(n+s)) functions, with the explicit gate-record count in the proof, by Counting bounded-size Boolean circuits.

Proof

technique · direct
1.1

Put s=2n/(10n) and let b be the fixed number of available gate types. The explicit encoding in [L1] gives at most (s+1)(n+s)(b(n+s)2)s circuits. Since b is constant, for all sufficiently large n the base-two logarithm is at most s(2n+O(1))+O(n)<2n/3.

L1givenalgebra
2.1

Dividing the resulting bound 22n/3 by the total 22n from [L2] gives at most 222n/3, which tends to 0. Hence a uniformly random truth table has size greater than 2n/(10n) with probability tending to 1.

L2step 1.1algebra
3.1

This is an existence-and-density argument over truth tables; it does not select or compute an explicit hard family.

step 2.1
DefinitionDefinition: Literature-sourcedProof: Not applicablejudge pass (gpt-5.6-terra)audited 2026-09-07Open item page →

Circuit satisfiability

Definition

CircuitSAT consists of well-formed finite topologically numbered Boolean gate lists with a designated output for which some input assignment makes that output one; malformed lists are rejected.

TheoremStatement: Literature-sourcedProof: AI-generatedprecheck passaudited 2026-09-07Open item page →

CircuitSAT is NP-complete

Statement

CircuitSAT is NP-complete under polynomial-time many-one reductions.

Facts & Assumptions

Given: the gate-list encoding of CircuitSAT.

[L1]

Well-formed gate lists have a designated output, and malformed lists are rejected, by Circuit satisfiability.

[L2]

SAT is NP-complete, by SAT is NP-complete.

[L3]

A polynomial-time many-one reduction must preserve membership in both directions, by Polynomial-time many-one reductions.

[L4]

NP-completeness means membership in NP together with NP-hardness, by NP-hard and NP-complete languages.

Proof

technique · direct
1.1

A verifier first rejects a malformed list. Otherwise it guesses one bit for every input gate, evaluates the gates in topological order, and accepts iff the designated output is 1. Its time is polynomial in the list length, so CircuitSATNP.

L1given
1.2

Given a Boolean formula φ, create one circuit input for each variable and one circuit gate for each connective, ordered from leaves toward the root; designate the root gate as output. This map is polynomial time and produces a circuit Cφ satisfying Cφ(a)=φ(a) for every assignment a. Therefore φSAT iff CφCircuitSAT, so [L2] and [L3] give NP-hardness.

L2L3givenconstruct
2.1

Combining membership from step 1.1 with hardness from step 1.2 proves NP-completeness by [L4].

L4step 1.1step 1.2
TheoremStatement: Literature-sourcedProof: AI-generatedprecheck passjudge pass (gpt-5.6-terra)audited 2026-09-07Open item page →

The Karp--Lipton collapse

Statement

If NPP/poly, then the polynomial hierarchy collapses to its second level: PH=Σ2p. Here Σ2p consists of languages expressible as xL    uvR(x,u,v) for a polynomial-time predicate R and polynomially bounded strings; Π2p reverses the two quantifiers, and PH is the union of the constant-alternation levels.

Facts & Assumptions

Given: NPP/poly.

[L1]

P/poly permits one polynomial-size circuit independently at each input length, by Circuit families and P/poly.

Proof

technique · direct
1.1

Let R(x,y,z) be any polynomial-time predicate with polynomially bounded z, and form the NP language ER={x,y,w:some extension zw satisfies R(x,y,z)}. By the hypothesis, ER has polynomial-size decision circuits. Successively querying whether the current prefix has a satisfying extension, first with a 0 appended and then with a 1 appended, composes polynomially many copies of these decision circuits into a polynomial-size search circuit. On input (x,y) for which some witness exists, it outputs an actual z satisfying R(x,y,z).

L1givenconstruct
2.1

Let LΠ2p, so xL    yzR(x,y,z). For each fixed input length, step 1.1 supplies a single polynomial-size search circuit C which works for every pair (x,y) of the relevant padded lengths. Therefore xL    C y  R(x,y,C(x,y)). If xL, choose the search circuit from step 1.1; conversely, any circuit satisfying the right side supplies the required witness for every y. The predicate merely evaluates C and checks R, so it is polynomial-time and the right side is a Σ2p formula.

L1step 1.1
3.1

Thus Π2pΣ2p; the reverse containment after complementing gives equality of the second levels. Replacing each inner Π2p block of a higher alternating formula by its Σ2p form and merging adjacent existential and universal blocks inductively collapses every constant-alternation level to Σ2p. Consequently PH=Σ2p.

step 2.1

5 · Examples, counterexamples and false statements

False statementConstruction: Literature-sourcedVerification: AI-generatedprecheck passaudited 2026-09-07Open item page →

Polynomial-size circuits imply a uniform polynomial-time generator

Statement

Every polynomial-size circuit family has a polynomial-time algorithm that, given 1n, outputs its length-n circuit.

Facts & Assumptions

Given: the nonuniform family convention.

[L1]

P/poly requires only a separate polynomial-size circuit at each length and no generator, by Circuit families and P/poly.

[L2]

There is an undecidable language recognized by constant-size circuits, by Some undecidable languages have polynomial-size circuits.

Refutation

technique · direct
1.1

Let (Cn) be the constant-size family for the undecidable length language from [L2]. If a polynomial-time generator G output Cn on input 1n, then on any word x one could compute G(1x) and evaluate that constant- size circuit on x in polynomial time.

L2givenconstruct
2.1

The resulting algorithm would decide the language, contradicting its undecidability. Hence this polynomial-size family has no such generator.

step 1.1contradiction
3.1

The size condition in [L1] is therefore strictly nonuniform; effective generation is an additional hypothesis.

L1step 2.1
False statementConstruction: Literature-sourcedVerification: AI-generatedprecheck passjudge pass (gpt-5.6-terra)audited 2026-09-07Open item page →

Shannon counting gives an efficiently explicit circuit-hard function

Statement

The Shannon counting argument itself gives a polynomial-time computable family of Boolean functions having exponential circuit complexity.

Facts & Assumptions

Given: the Shannon counting argument.

[L1]

Counting circuits gives only an upper bound on how many truth tables they represent, by Counting bounded-size Boolean circuits.

[L2]

The resulting theorem says that almost all truth tables are hard, by Almost all Boolean functions require exponential circuit size.

Refutation

technique · direct
1.1

The argument in [L1] and [L2] compares two cardinalities and concludes that the complement of the set of small-circuit truth tables is nonempty (and large). One can make an ineffective-for-complexity selection computable by enumerating every bounded-size circuit, forming all of their truth tables, and choosing the lexicographically first missing table. That exhaustive procedure, however, takes time exponential (indeed much larger) in the truth-table length and supplies no polynomial-time algorithm for evaluating the selected function on an input.

L1L2givenconstruct
2.1

Consequently the counting proof establishes existential hardness and even permits a brute-force computable choice, but it does not by itself produce an efficiently explicit hard family. Such a family requires an additional efficient construction and lower-bound argument absent from the count.

step 1.1
3.1

This distinction refutes the claim that the Shannon counting argument itself supplies a polynomial-time computable hard family.

step 2.1

Sources