HHL state-preparation and simulation access model

For a Hermitian $H$ on a finite-dimensional register, with operator norm as in The operator norm is zero on the zero domain and otherwise is max_{||v||=1} ||Tv||, the HHL access instance supplies: (i) a unitary $B$ with $B\mathrm{\mid }{0}_{I,W}⟩=\mathrm{\mid }b\mathrm{/}\mathrm{\parallel }b\mathrm{\parallel }{⟩}_I\mathrm{\mid }{g}_B{⟩}_W$ for a fixed normalized work state $\mathrm{\mid }{g}_B⟩$ (which may be $\mathrm{\mid }{0}_W⟩$) and declared costs for $B,B^{†}$ and any controlled forms used; (ii) for every requested real $t$ and tolerance $\eta$, a controlled simulation circuit $S_H(t,\eta )$ with operator-norm error at most $\eta$ from $e^{+iHt}$, and separately declared inverse/negative-time costs; and (iii) separate actual resource functions $C_B,C_{B^{†}}$, $C_{\mathrm{s}\mathrm{i}\mathrm{m}}(t,\eta )$, $C_{\mathrm{\Psi }}(T,{ϵ}_{\mathrm{\Psi }})$ for each forward or inverse sine-table preparation, $G_{\mathrm{\Psi }}(T,{ϵ}_{\mathrm{\Psi }})$ for its one-time classical table generation/data bits, $C_{\mathrm{Q}\mathrm{F}\mathrm{T}}^{+\mathrm{/}-}(T)$, $C_{\mathrm{f}\mathrm{l}\mathrm{a}\mathrm{g}}(\kappa ,{\eta }_R)$, $C_{\mathrm{a}\mathrm{r}\mathrm{i}\mathrm{t}\mathrm{h}}(T,\kappa ,ϵ)$, $C_{\mathrm{r}\mathrm{e}\mathrm{f}}$, and $C_{\mathrm{v}\mathrm{e}\mathrm{r}}$, and costs for reversible arithmetic, registers and finite-precision gate synthesis. Here $C_{\mathrm{Q}\mathrm{F}\mathrm{T}}^{-}$ is the negative-sign Fourier circuit and $C_{\mathrm{Q}\mathrm{F}\mathrm{T}}^{+}$ its positive-sign inverse, $C_{\mathrm{a}\mathrm{r}\mathrm{i}\mathrm{t}\mathrm{h}}$ is the per-attempt reversible decode/filter arithmetic cost, and $C_{\mathrm{r}\mathrm{e}\mathrm{f}},C_{\mathrm{v}\mathrm{e}\mathrm{r}}$ are the per-call reflection and well-verification costs. These functions count the stated circuit implementation in the chosen gate/access model; they assert no polylogarithmic bound on table generation or rotation synthesis. The positive exponential sign is the OP5 convention. An implementation of $H$ from matrix entries or a sparse oracle is additional data and must include its own proof and cost. A bare matrix, sparsity promise, or list of amplitudes is not a circuit. A rational scale $\mathrm{\Lambda }\ge \mathrm{\parallel }H\mathrm{\parallel }$ may be supplied; after replacing $H$ by $H\mathrm{/}\mathrm{\Lambda }$, the supported gap $\gamma$ gives $\kappa =\mathrm{\Lambda }\mathrm{/}\gamma$.

Clean-workspace simulation mode. The original full-operator-norm access mode remains admissible. Alternatively, supply a unitary dilation $S$ with a fixed clean-work embedding $J$ and $\mathrm{\parallel }SJ-J{e}^{+iHt}{\mathrm{\parallel }}_{\mathrm{o}\mathrm{p}}\le \eta$, including arbitrary timing/control/reference registers. The ideal operation leaves this simulator workspace in zero; other ideal HHL operations do not touch it. Actual output work may be dirty. Supply actual circuit inverses and controls and charge their full workspace and query costs. Unitary hybrids on a preserved clean-work subspace proves the same clean-input error for the actual adjoint, coherent controls and arbitrary references, and proves accumulation along the ideal all-clean trajectory. The inverse used in HHL uncomputation/amplification is the literal reverse physical circuit, not a separately approximated negative-time routine. Include simulator work in the joint output comparison and the ideal all-zero algorithm registers. A full-space error on arbitrary dirty inputs is neither required nor inferred in this alternative mode.