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These labels describe origin, not correctness: citations and verification chips remain separate evidence.

Generic Circuit Count Lower Bound

Statement

Fix a nonempty finite gate alphabet of A≥1 gates, each of arity at most k with 1≤k≤3, and count circuits on n≥1 classical input wires with zero-initialized ancillas and one designated measured output bit. No additional classical acceptance predicate is free. For a gate budget C≥n, put W=n+kC+1. After deleting unused ancillas, every such circuit has at most W wires, and there are at most W∑j=0C(AWk)j=exp⁡(O(Clog⁡C)) output-designated gate-list descriptions. Each description computes at most one Boolean function with success probability at least 2/3 on every input. Hence, for all sufficiently large n, at least 99% of Boolean functions on n bits require Ω(2n/n) gates. If arbitrary classical postprocessing is allowed, its circuit or description cost must be included; otherwise this conclusion need not hold.

Facts & Assumptions

Given: A fixed finite gate alphabet with A≥1 gates and maximum arity 1≤k≤3, n≥1 classical input wires, zero-initialized ancillas, and one designated measured output bit. Count circuits with at most C gate occurrences, where C≥n; delete unused ancillas, retaining the output wire, so at most W=n+kC+1 wires remain. The acceptance event is that measured bit being 1, with no free classical postprocessing.

[A1]

Finite circuit syntax and ordered wire labels gives finite ordered gate supports and chronological layers; Denotational semantics of a finite layered circuit gives the exact product denotation of those layers. Their current draft bodies were inspected. A layered circuit can therefore be serialized in its stated order with the same denotation.

[F1]

Quantum acceptance probability for a finite promise computation defines pC(x) as the probability of the designated accepting output event for the circuit and input.

[F2]

BQP for promise problems in the fixed QC14 model uses acceptance at least 2/3 on YES inputs and at most 1/3 on NO inputs.

[F3]

Finite circuit resource accounting defines circuit size as the number of gate occurrences and width as the number of all wires, including workspace.

Proof

1.1givenA1F3algebra

By [F3], gate budget C counts gate occurrences and W includes every workspace wire. A circuit with j gate occurrences has at most (AWk)j ordered gate-list descriptions on W wire labels: there are A gate types and at most Wk ordered supports per type. By [A1], flattening each finite layer list in chronological order preserves its denotation, so every layered circuit of at most C gates is represented by one of these lists. Choosing the designated output wire contributes a factor at most W. Thus the number of descriptions is at most W∑j=0C(AWk)j. Since A≥1, W≥1, C≥n, and k is fixed, W=O(C) for positive C and AWk≥1. The sum is at most (C+1)(AWk)C, whose logarithm is O(Clog⁡C). Duplicate denotations only reduce the number of computed functions.

1.2F1F2algebra

By [F1], a fixed description has one acceptance probability pC(x) at each input. If it computed two distinct Boolean functions with success threshold [F2], some input x would require the same number pC(x) to be both at least 2/3 and at most 1/3, which is impossible. Therefore one description accounts for at most one truth table.

2.1step 1.1step 1.2algebra

There are exactly 22n Boolean functions on n bits. For Cn=⌊c2n/n⌋, the bound in step 1.1 has base-two logarithm at most KCnlog⁡2Cn for a constant K depending only on the fixed alphabet and arity. Since log⁡2Cn≤n+O(1), choose c>0 so that this logarithm is at most 2n−1 for all sufficiently large n. Then the fraction with at most Cn gates is at most 22n−1/22n<0.01 eventually. By step 1.2, each description covers at most one function, so at least 99% require more than Cn=Ω(2n/n) gates. This is an almost-all lower bound, not a lower bound for each named function.

3.1givenstep 1.2step 2.1∎

The model in the statement charges the measured output-bit event and includes no free classical postprocessing, so the one-description/one-function count applies as stated. If a classical postprocessing circuit is admitted, it must be included in the finite description and gate count before this argument can be reused.

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