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TheoremStatement: Literature-sourcedProof: AI-adaptedPipeline-generated
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  • Literature-sourced: the exact statement appears in a cited source; only wording and notation differ.
  • AI-adapted: a semantically identical restatement of literature-sourced material, modulo indexing, notation, and boundary cases adopted by the library.
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These labels describe origin, not correctness: citations and verification chips remain separate evidence.

Amplitude Table Precision and Compilation

Statement

Let integer n≥0, D=2n, unit vector a∈CD, and integer b≥1 be given. Let v∈Q(i)D have each real and imaginary coordinate within 2−b of the corresponding coordinate of a. Put η=2D 2−b and assume η<1/2. Then v≠0 and ∥v/∥v∥2−a∥2≤2η. For n=0, the unique data ray is prepared by the empty circuit with zero error. For n≥1, prepare the normalized table v/∥v∥2 by QC24 State Preparation, and suppose its exact continuous circuit has an integer G≥1 of unitary blocks on the data and clean work register, each acting on at most a fixed integer k≥1 wires independent of n,D,G, with an integer s≥0 clean work qubits and G=O((n+1)D). For any 0<εc<1/2, choose a rational internal budget εc′ with εc/2<εc′<εc and compile each complete, unconditional block with projective operator-norm error at most εc′/G. Then the compiled joint output ray is within projective chord distance 2η+εc of [a⊗∣0s⟩].

For fixed block arity, the declared compiler interface yields O(Glog⁡c(G/εc)) finite-alphabet gates, with c=log⁡3/25. If the rational table v is supplied in a dense fixed-width encoding with b bits per real/imaginary coordinate, it has 2Db=Θ(Db) input bits; the preprocessing reads this encoding and computes the exact normalization internally. Table input and preprocessing are separate from coherent gate cost. The statement asserts no uniform bit-time for angle computation or SK compilation; the separate proposed supplier Finite-Precision Bit Complexity of the SU(2) Solovay–Kitaev Compiler and certified angle evaluation remain held obligations.

Facts & Assumptions

Given: A unit vector a, a rational table v, the error and block-compiler hypotheses in the Statement, an unconditional preparation circuit on n data qubits and its clean work register, and a fixed maximum block arity k≥1 independent of n,D,G.

[F1]

The preparation algorithm acts on an explicit table and produces the target ray by prefix rotations and leaf phases (QC24 State Preparation).

[F2]

Its exact circuit has G=O((n+1)D) bounded-arity gates (QC24 State Preparation Rotation Level Upper Bound).

[F3]

Projective chord distance is the infimum Euclidean distance over unit phases by definition, and this infimum is attained (QC24 Projective Chord Distance, Projective Chord Distance Formula).

[F4]

A rational table with a fixed-width encoding of b bits per real/imaginary coordinate occupies 2Db bits, and the model separates input scanning from quantum gate cost (QC24 State Preparation Cost Model).

[F5]

The Euclidean norm induced by the root inner product satisfies the triangle inequality (The inner-product norm is definite, homogeneous, and satisfies the triangle inequality).

[F6]

The operator norm is the maximum of ∥Tψ∥ over unit input vectors, and a unitary therefore has operator norm 1 (The operator norm is zero on the zero domain and otherwise is max_{||v||=1} ||Tv||).

[F8]

Between any two distinct real numbers lies a rational number (The rationals embed densely in the reals).

[F9]

The ordered tensor factors give an orthonormal product basis, and wire permutations permute that basis (Ordered tensor registers, their inner product, and wire permutations).

[A1]

Every block on r wires, 1≤r≤k, has an exact finite no-ancilla circuit over one-qubit U(2) gates and CNOTs; the stated QSD bound is at most 4r CNOTs for r≥2, and none is needed for r=1 (Exact QSD CNOT Upper Bound). Put Ck=4k and Mk=k+2Ck. Step 1.2 derives a uniform one-qubit factor bound from this CNOT bound by combining gates on each wire.

[A2]

The fixed-arity supplier Fixed-Arity Unitary Error Budget proves whole-block projective error and gate-count bounds for a supplied exact one-qubit/CNOT factorization. It accepts a real target error and uses a rational dyadic tolerance internally. No improved QSD CNOT count or compiler bit-time is inferred here.

Proof

Given: As in Facts & Assumptions.

1.1givenalgebra

Each of the 2D real coordinates differs by at most 2−b, so ∥v−a∥22≤2D 2−2b and ∥v−a∥2≤η. The reverse triangle inequality gives ∣∥v∥2−1∣≤η, hence ∥v∥2≥1−η>0.

1.2A1A2F1F2F8given

Use [F8] to choose a rational εc′ with εc/2<εc′<εc. Let the exact normalized-table circuit be UG⋯U1. Each block has positive arity rj≤k and, by [A1], an exact circuit with at most Ck CNOTs. Scan that circuit chronologically, maintaining one pending one-qubit product on each wire. At a one-qubit gate, compose it into its wire's pending product. Before each CNOT, emit the two pending products on its control and target and reset them to identity; pending products on other wires commute with that CNOT and may remain pending. At the end emit all rj pending products. This preserves the exact circuit product and uses at most 2Ck+rj≤Mk one-qubit factors, counting identities if necessary, so the one-qubit count is positive. Apply [A2] to this factorization with real target error εc′/G; it gives a compiled block U~j and a unit scalar λj with ∥Uj−λjU~j∥op≤εc′/G<εc/G. Each block includes all of its controls and targets before compilation; thus λj is a scalar on its entire support and becomes one global scalar when tensored with identities on the other wires.

2.1givenF5step 1.1algebra

Split the normalization error through v: by [F5], ∥v/∥v∥2−a∥2≤∥v/∥v∥2−v∥2+∥v−a∥2=∣1−∥v∥2∣+∥v−a∥2≤2η.

2.2F5F6F7F9step 1.2algebra

Insert the G intermediate products between UG⋯U1 and (∏jλj)U~G⋯U~1 to obtain the telescoping sum with one block difference in each term. Each support-level block difference, when extended by identity to the full ordered register, has operator norm at most its support norm: after permuting the product basis to group support and unused wires, write a vector as ∑txt⊗et in an orthonormal basis (et) of the unused wires, and use ∑t∥Axt∥2≤∥A∥op2∑t∥xt∥2. The wire permutation preserves norm by [F9]. For any unit input vector, [F5] bounds the norm of the telescoping sum by the sum of term norms; [F6] gives norm 1 for every surrounding unitary factor, so [F7] bounds each term by εc′/G. Taking the maximum over unit inputs with [F6] gives whole-circuit operator error at most ∑j=1Gεc′/G=εc′<εc. Applying this to the fixed initial vector gives projective chord error at most εc′ from the exact normalized-v output.

3.1F3F5step 2.1step 2.2algebra

By [F3], choose a phase aligning the compiled output to the exact normalized-v joint output within εc′, and a phase aligning that exact output to a⊗∣0s⟩ within 2η by step 2.1. Multiplying the second phase by the first and applying [F5] gives dch([out],[a⊗∣0s⟩])≤2η+εc′<2η+εc.

4.1A1A2F1F4step 1.2∎

For fixed maximum arity k, [A2] uses O(Mklog⁡c(MkG/εc′)+Ck) finite-alphabet gates per block at accuracy εc′/G. Since Mk,Ck are constants, εc′>εc/2, and G/εc>2, this is O(log⁡c(G/εc)) per block; hence G blocks use O(Glog⁡c(G/εc)) gates. If the rational input table v has an encoding as in [F4], it contains 2Db bits, and [F1] reads every real/imaginary coordinate in its preprocessing pass before exact normalization; this input scan is separate from quantum gate count. No angle-computation or compiler bit-time follows from these bounds.

Remarks

The compilation error is projective for each complete unconditional block. The exact QSD construction supplies the factorization needed by the fixed-arity compiler for every block in the stated arity bound. Rephasing a one-qubit gate before adding its control is not justified: that scalar becomes a relative phase between control branches. The separate bit-complexity supplier is not used as a premise here because no uniform bit-time claim is made.

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