QC24 State Preparation

Input and output. Input an integer $n\ge 0$ and an explicit exact table $(a_x{)}_{x\in \{0,1{\}}^n}$ in the ordered basis convention of Big-endian encoding of ordered bit strings. If the table length is not $D=2^n$ or ${\sum }_x\mathrm{\mid }{a}_x{\mathrm{\mid }}^2\mathrm{\ne }1$, return INVALID. Otherwise return a finite continuous-gate circuit which prepares the ray $[a]$ from $\mathrm{\mid }{0}^n⟩$, together with its classical angle table. When the table is supplied as a dense fixed-width bit encoding, read all $b$ bits of each real and imaginary coordinate before computation. Arithmetic is ideal and exact: it supplies complex arithmetic, absolute value, exact zero tests and square roots; for $x,y\ge 0$ not both zero, $\mathrm{atan2}(y,x)$ returns the unique $\varphi \in [0,\pi \mathrm{/}2]$ with $\cos \varphi =x\mathrm{/}\sqrt{x^2+y^2}$ and $\sin \varphi =y\mathrm{/}\sqrt{x^2+y^2}$. For $z\mathrm{\ne }0$, $\arg z\in (-\pi ,\pi ]$ is the unique principal angle in the polar form of Every nonzero complex number has a unique polar form $r(\cos \theta +i\sin \theta )$ with $r>0$ and $-\pi <\theta \le \pi$, so $z=\mathrm{\mid }z\mathrm{\mid }{e}^{i\arg z}$ by $\exp (x+iy)=e^x(\cos y+i\sin y)$, $\mathrm{\mid }\exp (x+iy)\mathrm{\mid }=e^x$, and $e^{i\pi }+1=0$. No Turing bit-time bound is asserted.

Exact gate-family operation model. Interpret this procedure's output in the ideal continuous-angle model with exact one-qubit gates $R_y(\theta )$ and $P_{\varphi }:=\mathrm{diag}(1,e^{i\varphi })$ for arbitrary real $\theta ,\varphi$, the two-qubit gate $C(R_y(\theta ))=\mathrm{diag}(I_2,R_y(\theta ))$ with the control first, and the fixed gates $X$ (The Pauli matrices) and Toffoli (Toffoli and Fredkin gates). Each occurrence of any of these gates costs one gate occurrence; the operation model explicitly grants controlled access to every $R_y(\theta )$ (Controlled Unitary Access). The phase gate is unitary since $\mathrm{\mid }{e}^{i\varphi }\mathrm{\mid }=1$ ($\exp (x+iy)=e^x(\cos y+i\sin y)$, $\mathrm{\mid }\exp (x+iy)\mathrm{\mid }=e^x$, and $e^{i\pi }+1=0$). This is an ideal parameterized gate-family model, distinct from a finite fixed-matrix alphabet. It does not assert that arbitrary-angle gates are exactly available from a finite alphabet or give their finite-alphabet cost.

Prefix norms and rotations. For every binary prefix $p$ of length at most $n$, set

$r_p=\sqrt{{\sum }_{x\text{ extends }p}\mathrm{\mid }{a}_x{\mathrm{\mid }}^2}\mathrm{.}$

For $\theta \in \mathbb{R}$ define

$R_y(\theta )=\left(\begin{array}{cc}\cos (\theta \mathrm{/}2)& -\sin (\theta \mathrm{/}2)\\ \sin (\theta \mathrm{/}2)& \cos (\theta \mathrm{/}2)\end{array}\right)$

in basis $(\mathrm{\mid }0⟩,\mathrm{\mid }1⟩)$. This is the $y$-axis rotation in the QC07 exponent convention; Pauli formula for an axis rotation gives this matrix and its unitarity. Define $C(U)=\mathrm{diag}(I_2,U)$ with the control as the first wire, following Controlled Unitary Access. For each $l=0,\dots ,n-1$ and each length-$l$ prefix $p$ in lexicographic order, skip the operation if $r_p=0$; otherwise set ${\theta }_p=2\mathrm{atan2}(r_{p1},r_{p0})$ and apply $R_y({\theta }_p)$ to bit $l$, controlled on the first $l$ bits equaling $p$. Length zero means no control. Thus no division is performed on a zero-norm branch.

Exact bounded-arity control construction. For a prefix rotation with $m\ge 2$ control bits, conjugate each zero-control bit by $X$ so the requested condition becomes all ones. Allocate $m-1$ clean work bits $w_1,\dots ,w_{m-1}$. Compute $w_1=c_1{c}_2$ with one Toffoli; for $j=3,\dots ,m$, compute $w_{j-1}=w_{j-2}{c}_j$ with one Toffoli. Apply $C(R_y({\theta }_p))$ to the flag and target bits, with the flag as the control, then apply the Toffolis in reverse order and undo the $X$ conjugations. For $m=1$, apply $C(R_y({\theta }_p))$ directly when the requested pattern is $1$; for pattern $0$, conjugate that controlled gate by $X$ on its control wire. For $m=0$, apply $R_y({\theta }_p)$ directly to the target bit. For a leaf phase with $m\ge 2$, use the same flag construction and apply $P_{\varphi }=\mathrm{diag}(1,e^{i\varphi })$ to the final work bit instead of a controlled rotation. A one-bit leaf phase uses $P_{\varphi }$ directly for pattern $1$ and $X{P}_{\varphi }X$ for pattern $0$. The work bits return to zero after each operation and are reused; no multi-control gate is assumed as a primitive.

Leaf phases. For a basis string $x$, define $P_{x,\varphi }=I+(e^{i\varphi }-1)\mathrm{\mid }x⟩⟨x\mathrm{\mid }$. Let $x_{\ast }$ be the lexicographically first index with $a_{x_{\ast }}\mathrm{\ne }0$. Put ${\varphi }_{\ast }=\arg (a_{x_{\ast }})$. For each other $x$ with $a_x\mathrm{\ne }0$, put ${\varphi }_x=\arg (a_x)-{\varphi }_{\ast }$ and, unless ${\varphi }_x\equiv 0(\mathrm{m}\mathrm{o}\mathrm{d}2\pi )$, apply $P_{x,{\varphi }_x}$ using the control construction above. The reference leaf needs no phase, and zero entries and zero relative phases require no gate. Every nonzero output amplitude is then $e^{-i{\varphi }_{\ast }}{a}_x$, including the reference leaf, so the output is the target ray. When $n=0$, the valid table has one unit-modulus entry and the empty circuit already prepares its unique ray.