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QC24 State Preparation Rotation Level Upper Bound

Statement

For an integer n≥0, D=2n, and a normalized explicit amplitude table, QC24 State Preparation exactly prepares the target ray using at most D−1 prefix rotations and at most D leaf phases. The specified Toffoli flag chain expands each operation into O(n+1) bounded-arity gates using at most max⁡{n−1,0} reusable clean work bits, so the complete circuit has O((n+1)D) gates and serial depth, in addition to the n data qubits. For n=0, the ray is trivial and no gate is needed.

Facts & Assumptions

Given: The exact algorithm, a normalized table (ax), and D=2n.

[F1]

The algorithm applies prefix rotations with angles determined by the child subtree norms, uses the stated clean Toffoli flag chain, and applies each nonzero relative leaf phase after subtracting the reference argument (QC24 State Preparation).

[F2]

At a positive-norm prefix, the rotation half-angle has cosine and sine equal to the child-radius ratios (QC24 Prefix Norm Rotation Identities).

[F3]

Toffoli maps ∣a,b,t⟩ to ∣a,b,t⊕ab⟩ and preserves its two control bits (Toffoli and Fredkin gates).

[F4]

A controlled operation on a control-first register applies its target unitary exactly on the control-1 subspace and the identity on the control-0 subspace (Controlled Unitary Access).

[F5]

The Pauli matrix X interchanges computational basis vectors, X∣c⟩=∣1−c⟩ for c∈{0,1} (The Pauli matrices).

[F6]

The ordered bitstring encoding places table entry ax at basis vector ∣x⟩ (Big-endian encoding of ordered bit strings).

[F7]

In the algorithm's convention, Ry(θ) has first column (cos⁡(θ/2),sin⁡(θ/2))T and is unitary (Pauli formula for an axis rotation).

[F8]

The ordered computational basis is orthonormal (The computational basis is orthonormal).

[F9]

A finite layered circuit denotes the chronological product of its local gate embeddings (Denotational semantics of a finite layered circuit).

Proof

Given: As in Facts & Assumptions.

1.1givenF1

Before any rotation the only nonzero prefix amplitude is the empty-prefix amplitude 1=r∅ because the table is normalized.

1.2F1F3F4F5F7F8F9F10givenconstructinduction

Consider a computational-basis control word c1,…,cm. Conjugating each zero-control by X turns the requested pattern into all ones by [F5]. Starting from zero work bits, [F3] first sets w1=c1c2 and then, successively, wj−1=wj−2cj; induction on j shows the final flag is 1 exactly on the requested control pattern. The controlled operation in [F4] therefore acts only on that branch and changes neither the controls nor the flag. The basis action [F3] shows each Toffoli is its own inverse, and [F5] shows X is its own inverse, so reversing the Toffoli list and undoing the X conjugations restores all work bits to zero. For a leaf phase, the phase gate is diagonal and also leaves the flag's bit value unchanged. For one control the direct controlled block has the same branch action, and for no controls the one-qubit block acts on every branch. The Toffoli and X are basis permutations, the rotations are unitary by [F7], and controlled blocks are unitary by [F4]; the phase gates are unitary by [F10]. The basis calculation extends linearly to superpositions under [F8] and [F9].

2.1F1F2F6F7F8F9step 1.1step 1.2algebracases

Suppose at depth l every prefix p has amplitude rp on ∣p0n−l⟩ under the basis order in [F6]. If rp>0, [F1], [F2], and [F7] split that amplitude into the nonnegative real amplitudes rp(rp0/rp)=rp0 and rp(rp1/rp)=rp1 on the two child prefixes. Step 1.2 shows the rotation is confined to the selected prefix branch; distinct length-l prefixes therefore leave each other's amplitudes unchanged. If rp=0, both children have radius zero and the zero branch remains zero without division. Thus induction gives the nonnegative real leaf amplitude rx=∣ax∣ at every leaf.

3.1F1F10step 1.2step 2.1algebra

Put ϕ∗=arg⁡(ax∗) for the first nonzero leaf. For every other nonzero leaf, [F10] gives ei(arg⁡(ax)−ϕ∗)∣ax∣=e−iϕ∗ax. The reference leaf has unchanged amplitude ∣ax∗∣=e−iϕ∗ax∗, so the same scalar multiplies every nonzero coordinate. A zero relative phase needs no gate. Its flag ladder restores the work bits by step 1.2, and a diagonal phase leaves the flag's bit value unchanged. Zero leaves stay zero. Thus the joint output is e−iϕ∗a⊗∣0s⟩ with the reused workspace zero, and its data ray is exactly [a].

4.1F1step 1.2givenalgebracases∎

The number of prefixes at depths 0 through n−1 is ∑l=0n−12l=D−1, and there are at most D leaf phases. A control of m≥2 bits uses 2(m−1) Toffolis, at most 2m X gates for zero-control conjugations, and one controlled one-qubit block; it uses m−1 clean work bits. Prefix rotations have m≤n−1 controls and leaf phases have m=n, so the maximum work count is max⁡{n−1,0}; the m=0,1 cases use constant resources. Since m≤n, each of at most 2D−1 operations costs O(n+1) gates and serial depth, and step 1.2 shows the same work bits are restored and reused. For n=0, both operation lists are empty and the normalized one-entry table has a single ray.

Depends on

Used by

Cited to discharge well-definedness by QC24 State Preparation.

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