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Quantum Fourier-Transform Circuits — Examples

1 · Prerequisites

2 · Summary

The two-qubit example writes the positive-sign N=4 transform in both wire orders, checks the final swap and exact gate count, and computes the one-level truncation error by the single omitted controlled phase. It is a finite check of the A-page conventions and formulas, including the exact three-CNOT SWAP expansion. Its gate-list interpretation and resource count use the batch-9 circuit-semantics and resource-accounting suppliers, which are present as drafts; readiness remains conditional on their review and acceptance.

3 · Logical flowchart

4 · Definitions, theorems and proofs

None yet.

5 · Examples, counterexamples and false statements

ExampleConstruction: Literature-sourcedVerification: AI-adaptedjudge pass (gpt-6-luna)Open item page →

QFT circuit order and truncation examples

Example

For N=4 (n=2), the positive-sign exact circuit in standard wire order q1,q0 is H(q1), then CP2(q0,q1), then H(q0), then SWAP(q1,q0). Its matrix in basis order ∣00⟩,∣01⟩,∣10⟩,∣11⟩ is

F4+=12(11111i−1−i1−11−11−i−1i).

If the same register is displayed in reversed wire order q0,q1, the matrix in that order is PF4+P, where P swaps the middle two basis vectors:

PF4+P=12(111111−1−11−1i−i1−1−ii).

With cutoff m=1, the only controlled phase CP2 is omitted, while the two Hadamards and final swap remain. The exact circuit has 2 Hadamards, one controlled phase and one SWAP (4 ideal gates, or 6 gates after expanding the SWAP); the truncated circuit has 2 Hadamards and one SWAP (3 ideal gates, or 5 with that expansion). Its operator-norm difference from the exact circuit is 2, and the general omitted-gate sum is π/2 for this n,m.

Facts & Assumptions

Given: Two ordered qubits, the Hadamard and controlled-phase matrices below, the positive-sign N=4 Fourier matrix, and the wire-swap permutation.

[L1]

The gate matrices are H=2−1/2(111−1) and CP2=diag⁡(1,1,1,i) from QFT ideal and finite-set gate-cost models.

[L2]

The exact chronological gate list and the cutoff-1 deletion are those in Exact binary QFT circuit and Truncated binary QFT.

[L3]

The positive-sign QFT formula at N=4 gives basis amplitudes (F4+)y,x=12eπixy/2 in binary basis order 00,01,10,11 (Positive-sign cyclic quantum Fourier transform).

[L4]

P is the permutation matrix exchanging ∣01⟩ and ∣10⟩ and fixing ∣00⟩,∣11⟩.

[F1]

The A-page lemma proves 2<π/2 from the cosine series (The half-turn constant exceeds 2).

[F2]

A SWAP on two ordered qubits equals the exact three-CNOT circuit (A SWAP Is Three CNOTs).

[F3]

The ideal QFT gate-count model assigns one count to each Hadamard, controlled phase and named SWAP (QFT ideal and finite-set gate-cost models).

[F4]

A gate on specified wires has a unitary global embedding that acts by the local gate there and by identity elsewhere (A local gate has a unique global wire embedding).

[F6]

Euler's formula gives eiθ=cos⁡θ+isin⁡θ for real θ (Euler's formula: exp⁡(iθ)=cos⁡θ+isin⁡θ for every real θ).

[F7]

The quarter-turn values include sin⁡(π/2)=1, cos⁡(π/2)=0, sin⁡π=0, cos⁡π=−1, with the shift identities used at 3π/2 (Quarter-turn values and shifts by pi/2 and pi).

[F8]

On a nonzero finite-dimensional domain, the operator norm is the maximum over unit vectors (The operator norm is zero on the zero domain and otherwise is max_{||v||=1} ||Tv||).

[F10]

The ordered product basis of the two-qubit register is orthonormal (The product basis is orthonormal and tensor dimensions multiply).

[F11]

For cutoff m=1, the operator-norm estimate sums (n−s+1)2π/2s over s=2,…,n (Operator-norm error of QFT truncation).

[F12]

The complex exponential satisfies exp⁡(z+w)=exp⁡zexp⁡w (exp⁡(z+w)=exp⁡z exp⁡w, and the complex exponential extends the real exponential).

[L5]

Kets denote vectors, and the standard-basis kets are coordinate vectors (Dirac Notation Conversion).

[A1]

Denotational semantics of a finite layered circuit identifies the chronological gate list with the right-to-left product of its embedded gate operators.

Verification

technique · direct finite calculation

Given: The two-qubit gate lists and conventions in [L1]–[L4].

1.1L1L2L3L5F4F6F7F12A1algebra

On basis input ∣x1x0⟩, after H(q1) and CP2(q0,q1) the q1 factor is 2−1/2(∣0⟩+(−1)x1ix0∣1⟩); after H(q0) the q0 factor is 2−1/2(∣0⟩+(−1)x0∣1⟩). The local gate actions are [F4], and their composition in chronological order requires [A1]. Euler's formula and the quarter-turn values [F6,F7] give eiπ/2=i, eiπ=−1, and e3πi/2=−i. For the nonnegative integer xy, iterating [F12] gives eπixy/2=(eiπ/2)xy=ixy, with both sides 1 when xy=0. After the final swap the factors are ordered as the q0 factor followed by the q1 factor. Substituting x1x0=00,01,10,11 gives the four columns [1,1,1,1]T, [1,i,−1,−i]T, [1,−1,1,−1]T, and [1,−i,−1,i]T, each divided by 2; these are the amplitudes in [L3].

1.2L1L2L5F1F4F5F8F9F10F11A1algebra

By [L2,A1], the difference of exact and cutoff operators is SH(q0)(CP2−I)H(q1), where the left and right factors are unitary: H∗H=I, CP2 is diagonal with unit-modulus entries, and S permutes an orthonormal basis [L1,F5,F9,F10]. Thus left multiplication preserves norms and right multiplication maps the unit sphere onto itself, so the difference has operator norm ∥CP2−I∥ by [F5,F8]. Write a unit vector as v=∑a,b∈{0,1}cab∣ab⟩. By [F10], ∑a,b∣cab∣2=1. The operator CP2−I sends v to (i−1)c11∣11⟩, and [F9] gives ∣i−1∣2=(i−1)(−i−1)=2. Hence ∥(CP2−I)v∥2=2∣c11∣2≤2, with equality at v=∣11⟩; [F8] gives ∥CP2−I∥=2. The bound in [F11] is (2−2+1)2π/22=π/2 for n=2,m=1, and [F1] gives 2<π/2.

2.1L3L4L5A1step 1.1algebra

Reversing the displayed wire order permutes both the input and output basis by P, so the matrix is PF4+P by the tensor-register convention [L4]. Swapping rows and columns 2 and 3 gives 12(111111−1−11−1i−i1−1−ii), which is the displayed reversed-order matrix.

3.1L1L2F2F3algebra∎

The exact list has 2+1+1=4 ideal gates, and its one SWAP adds three CNOTs by [F2]; the ideal convention is [F3]. The cutoff list has 2+1=3 ideal gates and the same three-CNOT expansion. Neither circuit introduces an ancilla.

Sources